Source oscillator frequency multiplier by 12000

Hi flatmax,

PLLs only work when you provide them with enough reference cycles for a decent comparison. While there's some work being done with digital PLLs to minimize the time to lock to low-frequency signals, none of the DPLLs we could give you would be good choices for this kind of wide-reference application. You could build your own in an FPGA, but something tells me this is beyond the scope of what you want to do.

From a PLL standpoint, you'd be much better off if you could establish a much-higher fixed-frequency and mix up the 0-5kHz signal so that the loop bandwidth of the PLL could support the desired rate of change. For example: if you can mix the 0-5kHz signal onto a fixed 100kHz oscillator, then multiply this signal up by a factor of 12k, your output would be a 1.2GHz signal with up to 60MHz of error. You could run a parallel PLL with a 12k multiplication factor off the same 100kHz oscillator but without the mixed-up 0-5kHz signal, and the result would be a fixed 1.2GHz signal with no error. Then you could mix the 1.2GHz + error with the 1.2GHz fixed and extract a 0-60MHz clock, which would continuously shift in frequency directly proportional to the 0-5kHz reference.

You could also break this up into a few stages, so that you're not multiplying up by a factor of 12k in a single PLL (this would cause lots of issues with cycle slip at the phase detector). Conceptually you can use the same scheme cascaded so you're only multiplying up by a factor of 100 and 120 in two stages - this requires more components and more PLLs, but there's virtually no concerns with cycle slip and the reference oscillators can be more realistic e.g. 10MHz. This also minimizes the tuning range required at each VCO.

All that said: given that the frequency range is 0-5kHz, there isn't too much that can be done about jitter cleaning with this approach since by definition we have to be tracking the 1-2kHz/s change in reference frequency (corresponding to at least 5kHz loop bandwidth, ideally more like 10kHz) - we can't adequately filter the sideband without tracking it, and we can't track it without keeping the loop bandwidth too high to filter it. Multiplying up by a factor of 12k also means multiplying up the jitter by a factor of 12k, so your clock signal will be pretty terrible quality even if you can get this approach working (at least as far as an audio ADC/DAC is concerned). Am I correct in inferring that your reference oscillator is basically a tachometer from the reference platter? I strongly doubt you could generate a clean enough clock from a motor signal, regardless of the flywheel effects that should theoretically be filtering transient noise, because the 1/f inherent in the motor drive for thermal reasons is going to be too high in-band (especially once multiplied up by 12k). Do not underestimate the effect of this 12k factor on the jitter: the whole signal's phase noise will increase by 20 * log(12k) = more than 80dB in-band, and it's not great to begin with. The induced phase error will be audible at steady state if the audio clock is coming from a motor drive. On the other hand, if your reference signal is synthesized from some high-quality source and is a software-generated proxy for the motor speed, this could work well - but at that point there's a more direct approach.

I think what you really want is the ability to rapidly and accurately predict the platter frequency from a limited number of samples. I don't think you need to directly couple the platter to the clock, and for the reasons stated above it tends to be a tough sell anyway. On the other hand, you can dictate the flywheel dynamics and you can probably sense the force being applied to it with some kind of magnetic field monitoring or back EMF sensing. If you can sample these signals really fast, you could come up with a model of the predicted angular velocity of the platter, and use it to dynamically adjust the frequency output of a DDS. This approach has some error, but if you can update the DDS faster than audio frequency you should be able to push the quantization error above the audio cutoff, leaving only the model error in-band. And since you're sampling really fast, you can continuously update the model and generate better coefficients at all times. The control loop here is more complex, but the benefit is you can use a fixed-frequency and low-jitter reference source for your DDS, so your frequency-sensing scheme no longer adds to the clock noise on the Audio ADC/DAC. And if your processor doing the modeling is fast enough, this is still a real-time control loop rather than high-latency post-processing in a DSP. Unfortunately, this would burden the CPU unless offloaded to a dedicated controller; and high-performance DDS is not exactly low-power or low-cost.

Maybe there's a hybrid approach where you switch signals between a very clean 1kHz while the platter is at nominal frequency, and something like the synthesizer/mixer approach described above while the platter is being manipulated. You still have a low-quality clock driving the audio source during frequency shifting, but unless you apply a near-constant force to the platter to induce a specific pitch shift, perhaps the act of variably shifting pitch itself may end up making the clock quality issues less audible. Personally I doubt that it would work like this, but that's just a gut feeling - it is otherwise something to consider.

Very neat idea, with a lot of interesting challenges to solve.

Regards,

Derek Payne