AFE7900EVM: Regarding the 4 simultaneous ADC channel I,Q output to ZCU102

Hi David,

Thank you for the response. 

As I have gone through the JESD interfacing guide (https://www.ti.com/lit/wp/sbaa517/sbaa517.pdf?ts=1655265779242&ref_url=https%253A%252F%252Fwww.google.com%252F) to understand the basic difference between JESD204B and JESD204C. What I understand is that JESD204C is is more advanced version with the high speed lane rates. 

As our main requirement is to use 4 simultaneous ADC channels with FPGA an receive simultaneous samples at the same time and for future use, we could also use another AFE7900EVM with Single ZU102 to increase the simultaneous 4 channels to 8 ADC channels.

Our main requirement is to use each ADC with a min possible sample rate which is 1500 MSPS and max decimation rate which is 48X , so that we could have the lowest possible output rate for I and Q for each ADC , which is 31.25 MSPS.

Also, for simultaneous samples arrival at FPGA , total I,Q rates for 8 channels would be 500 MSPS and for 4 channels would be 250 MSPS . 

So, As both JESD204B and JESD204C have deterministic latency enable option available. Can you please suggest which interfacing standard JESD204B or JESD204C would be more suitable to our above requirement ?