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AFE7900: ADC JES204 Link Problems

Suleyman Taha Secen
Prodigy 35 points
Part Number: AFE7900

Figure1. 

I have a custom board design with AFE7900 and Xilinx Xcku050 FPGA.  

Figure 1 shows that the FPGA-AFE connection in my design. 

All Xilinx JESD204 IP are configured as LMFS=1-4-8-1-0, K=4, and LaneRate=10 Gbps. core_clk frequency is 250 MHz.  

I wanted to configure AFE7900 2-link 1-4-8-1-0 configuration. Lane Rate is 10 Gbps. 

After FPGA starts the configuration steps which are created in Latte Scripts. (it's in attached files.)

I check the Xilinx IP gt0_rx signals in ILA but I haven't seen the h'BCBCBCBC in gt0_rx signals.

Because of that the FPGA RX IP's don't complete the SYNC process.

Why the FPGA does not catch the h'BCBCBCBC characters in SERDES line?

I don't know how to debug this. 

Could you give me advice on this problem?

Best Regards. 

Stsecen

  • 0
    TI__Genius 10655 points

    Hi Stsecen,

    Did you test the script you are using on a TSW14J5xEVM? I don't see an attachment in your post. 

    Are you aware of TI JESD IP that facilitates easier integration with TI JESD parts? You can find more detials here: https://www.ti.com/tool/TI-JESD204-IP

    Regards,

    Vijay

  • 0 in reply to Vijayendra Varma Siddamsetty
    Prodigy 35 points

    6663.Afe79xxPg1_Case3.txtHi Vijay, I shared the scripts. I tested the script on EVM. It works correctly. 

    070000011903 [8] = SRX1/5 LOS indicator Bit1 --> for DAC_JESD_CD

    In SPI configuration, there is error occured the DAC_JESD_CD 119th Register. In Alarm Register, SRX1/5 LOS indicator bit was high. 

  • 0 in reply to Suleyman Taha Secen
    TI__Genius 13920 points

    Hi Suleyman,

    Can you confirm that you are selecting the appropriate pins on the FPGA for SRX5? The LOS indicator is pointing to a possible issue with the lane configuration either on the AFE side or the FPGA side. 

    Regards,

    David Chaparro

  • 0 in reply to David Chaparro
    Prodigy 35 points

    Hi David, 

                          Figure 1.   Latte Configuration

    The configuration is shown in Figure 1. 

     I and my colleagues double-checked board schematic. 

    The sync signals are sometimes asserted when the board re-power up and the signal often stays logic high about 10 seconds, but mostly they are logic low. 

  • 0 in reply to Suleyman Taha Secen
    Prodigy 35 points

    Hi David,

    I have also three questions

    1- The custom board has 5 GHz clock source. I can check to clock source chip status. It seems that the clock source is ok. But, when I read Register 15F'h on the JESD_SUBCHIP page, AFE returns 0x03. The register indicating SerdesAB and SerdesCD PLL loss-of-lock. How should I understand this? Is there any register in AFE to report the external clock status?

    2- How can I read the single register with using Latte scripts? I want to compare some registers value on EVM with my design.

    3- I need to change NCO1 and NCO2 values for all TX-RX channels on runtime. I aim to create a graph by trying it in different frequency ranges. I want to change the NCO frequencies by writing command on SPI. Could you share me a both RXTOP and TXTOP registers write sequence to change NCO frequency?

    Best Regard,

    stsecen

  • +1 in reply to Suleyman Taha Secen
    TI__Genius 13920 points

    Hi Suleyman,

    1- When using an external clock we do not have a register to check if the clock is present. One thing to try is to set the DAC into constant test pattern mode. This will mean that the DACs will output only the NCO frequency without the need of data from the FPGA. If the output is present then we would know that the clock is getting to the AFE. To put the DACs into this mode you can use the following command in Latte:

    for i in [0,1]:
         for j in [0,1]:
              AFE.JESD.DACJESD[i].dacJesdConstantTestPatternValue(1,j,0,16384,0) # enable, channelNum, bandNum, Ival, Qval

    2- To write directly to registers you can use the device.writeReg(Addr,Data) command. To read you can use device.readReg(Addr).

    3- The NCOs can be updated two ways, writing directly to the NCO registers or using the update NCO macro. The registers for both of these options are given in the Register Set document, SBAU337, which is available in the AFE79xx secure folder.

    Regards,

    David Chaparro