AFE7900EVM: 8b10b SYNCBIN design error (when connected to ZCU102 board)?

In the AFE7900EVM schematic:

• Page 9. SYNCBINP0, SYNCBINM0 connect to the FMC connector on page 19 at pins G12 and G13.
• The other SYNCBINs and BOUTS connect to H34,H35; F10,F11; and F19,F20.

Switching to the ZCU102 schematic:

• Pages 35-36: H34,H35; F10,F11; and F19,F20 are all No Connects.
• G12 & G13 are named FMC_HPC1_LA08_P/N which connect to pins AF3 (LA08_N) and AE3 (LA08_P).

In the FPGA reference design ZCU102_AFE79xx_8b10b_10Gbps DesignFiles/constraints.xdc:

• adc_rx_sync_n is wired to AE3 as an LVCMOS18
• dac_tx_sync_n is wired to AF3 as an LVCMOS18

And finally, in the same reference design, DesignFiles/TI_204c_IP_ref.sv:

• output wire adc_rx_sync_n
• input wire dac_tx_sync_n

There seem to be four problems:

1. These lines at LVCMOS18 will send 1.8V to a 1.2V LVDS buffer on the AFE.
2. SYNCIN is a differential input on the AFE, but connected to separate CMOS lines on the FPGA.
3. dac_tx_sync_n is an input on the FPGA connected to an input on the AFE.
4. SYNCBOUT is not connected to anything (even though presumably dac_tx_sync_n should be)

I'm trying to understand how SYNCBIN vs SYNCBOUT need to be wired to the FPGA. My guess is that SYNCBIN should be an LVDS at 1.2V run to an LVDS 1.2V output at the FPGA connected to adc_rx_sync_n, while SYNCBOUT should be an LVDS 1.2V run into an LVDS 1.2V input at the FPGA connected to dac_tx_sync_n.

Is this an error? Am I missing something? 

Thanks!