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AFE7920: AFE7920 ADC FPGA to JESD Pass Test

jaesun do
Prodigy 20 points
Part Number: AFE7920

i'm bringup afe7920 with xilinx zynqmp.

In latte, we got the settings we wanted and
ZYNQMP wrote the settings to the AFE7920 via SPI.
But the data coming from the AFE7920 to the FPGA is unchanged.

rx_jesd

So I wanted to send something like a test pattern from AFE7920 via SPI settings and when I looked at the register map, I found the following registers.

If you look at the ADC register map, you will see the registers for the test pattern from 109 to 11B.
So I set the values as below and did not see any change in the values when viewed through FPGA ILA.
Is there something I am missing or setting incorrectly?

write 0016 01
write 010c 01
write 010d 12
write 010e 34
write 010f 56
write 0110 78
write 0111 9a
write 0112 bc
write 0113 de
write 0114 f0
write 0115 10
write 0116 32
write 0117 54
write 0118 76
write 0119 98
write 011a ba
write 011b ed
write 0109 01 or 02
write 010a 01 or 02
write 010c 01 or 02

write 0016 02
write 010c 01
write 010d 12
write 010e 34
write 010f 56
write 0110 78
write 0111 9a
write 0112 bc
write 0113 de
write 0114 f0
write 0115 10
write 0116 32
write 0117 54
write 0118 76
write 0119 98
write 011a ba
write 011b ed
write 0109 01
write 0109 01 or 02
write 010a 01 or 02
write 010c 01 or 02

  • 0
    TI__Guru 66204 points

    Hello Mr. Do,

    Please help check if the RX signal check is in normal operation mode as oppose to low power saving mode during bring-up. You can use C API overrideTdd() to enable the RX chain to normal mode and check if the JESD204 data is in normal operation.

    In low power saving mode, the JESD204 link is still established, but the AFE79xx is sending out zero pattern from the RX chain to your FPGA, and perhaps explains the unchanged code.

    -Kang

  • 0 in reply to Kang Hsia
    Prodigy 20 points

    I added overrideTdd(0,0xf,0x3,0xf); to the source code, but I still don't see any change in the data. Is there any way to check if the FPGA JESD and AFE7920 are connected properly?

  • 0 in reply to jaesun do
    TI__Guru 66204 points

    Hi Mr. Do,

    You may use the function adcRampTestPattern to generate a ramp pattern to observe 0 to 65535 code for all 16-bit from the ADC. Please see if you can see a match on your FPGA capture.

    The JESD204 link has the JESD204 receiver to determine the success of the link-up and error interpretation. Since the FPGA is the JESD204 receiver, please utilize the Xilinx IP error readout to check the success of the JESD204 handshake/link-up

    -Kang