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Original question:

AFE7950: AFE7950 bring-up time

AFE7950: Intermittent JESDC elastic buffer overflow (bad RBD value) errors during AFE initialization

Joshua Wright
Prodigy 10 points

Part Number: AFE7950

We have a custom design with an AMD Versal connected to a TI AFE7950. The Versal contains an AMD JESD204C Transmit core, which we are sending IQ sine/cosine data from a LUT. The issue is that it appears to have a 50/50 chance of coming up without any errors during the AFE configuration, but the other half of the time I see multiple alarms and errors that seem to be consistently related to a bad RBD value.

The RBD value generated from Latte (shown below) is 4. I ran through the calculation documented in TI SBAA543 from reading the lane counters, which all read back as 0:  RBD = (0 + 4) % (64 *1) = 4 % 64 = 4

The calculated RBD value appears to match the value from Latte, though the intermittent link initialization failures seem to indicate a bad RBD value. I was curious if you had any suggestions on how to debug/investigate further.

We have done PRBS31 link testing between the FPGA and AFE at 16.5 Gbps using AMD's IBERT tools, and did not see any errors detected. The captured eyes also looked good.

The other question I had is if you had the SPI commands to run the CAFE adcDacSync command? I see it referenced, but we don't have a direct connection to the AFE and PC, so we are sending SPI commands via the FPGA.

Latte JESD_RX Configuration

  • 0
    TI__Expert 5225 points

    Hi Joshua,

     Sorry for the delay on this. Here are some suggestions: 

    1. In regards to getting the SPI commands from Latte for the adcDacSync. You can get these writes for your specific mode by doing the following in the Latte GUI.
      1. Run setup.py, devinit.py and your configuration file as normal.
        1. Your configuration file must have "logDumpInst.logFormat=0x1"
        2. This will create a log file like you are familiar.Make sure to take note of the last line of the file at this step.
      2. If you then run the AFE.adcDacSync(1) function in the command line tyou will see that thewrites for adcDacSync for your specific mode will be in the log file.
      3. You can then use these writes as adcDacSync for your particular mode.
    2.  Is the SYSREF synchronised with respect to the AFE Fref clock and the FPGA clocks?
    3. Could you make sure the phase of SYSREF is stable in relation to the AFE Fref clock and the FPGA clocks?
    4. Could you please check the all_lane_ready counters for all the lanes to make sure all the lanes are being registered as ready and recalculate your RBD?
    5. Have you also tried using a sligthly higher RBD value to see if the link comes up reliably?

     Best,

     Camilo