Tool/software:
Our design has a problem initializing the JESDI interface between TI FPGA IP and the AFE7950 ,reliably. The ADC side of the JESDI interface is failing to initialize reliably about 50-60% of the time.
The signaling on the ADC JESDI RX interface in the FPGA displays as shown below in the included image(first image) when it fails.
The rx_sync_reset is held asserted while the 7950 initializes, but on completion of the AFE initialization and release of rx_sync_reset the receive interface doesn’t seem to be syncing and won’t start up.
From the image below it can be observed that the ila_rx_data_valid never goes high and the rx_sync_n never goes high . However it can be seen that the lmfc pulse trains realigns just at the point where the sysref align count goes from 0 to 1. Also there is zero errors in the error counters.
The included failing image (second image) is what we see when the initialization completes correctly (See below) :
So how can we diagnose what is causing the initialization to fail? Is there any status that can be probed on the testports 1,2,3 on the TI FPGA IP core that can provide some insight as to why the failing sequence above occurs ?
Also is there an update to the IP JESDI core?
Thanks
Joe
