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AFE7950: A couple of MACROs are not completing, but are not documented.

David Caruth
Prodigy 60 points
Part Number: AFE7950

Tool/software:

Hello,

I am running the output of a Latte log with an AFE7950 using not continuous sysref and am getting a couple of errors due to MACRO_DONE not getting set after running a MACRO at two different points in the code.  The MACRO opcodes are not documented and I can't tell from the comments what is being attempted with the MACROs.

Here's an excerpt for the first case of MACRO_DONE not getting set (lines 1718-1737):

SPIRead 00f0,0,0

//Read MACRO_READY=0x1; Address(0xf0[7:0])


SPIPoll 00f0,0,0,01
SPIWrite 00a3,00,0,7 //MACRO_OPERAND_REG0=0x1; Address(0xa0[7:0],0xa1[7:0],0xa2[7:0],0xa3[7:0],0xa4[7:0])
SPIWrite 00a2,00,0,7
SPIWrite 00a1,00,0,7
SPIWrite 00a0,01,0,7
SPIWrite 0193,78,0,7 //MACRO_OPCODE=0x78; Address(0x193[7:0],0x194[7:0])

WAIT 0.001
SPIRead 00f0,2,2

//Read MACRO_DONE=0x1; Address(0xf0[7:2])


SPIPoll 00f0,2,2,04
SPIReadCheck 00f0,3,3,00

The final SPIReadCheck fails.  Any idea why MACRO_OPCODE=0x78 would not complete?

If I comment out the failing SPIReadCheck, the code can make it to later in the programming, where a similar error occurs, but for a different MACRO_OPCODE.

Here's the excerpt (lines 3529-3551):

//START: Configuring TX Chain Parameters to TOP MCU

SPIWrite 0018,20,0,7 //macro=0x1; Address(0x18[7:5])
SPIRead 00f0,0,0

//Read MACRO_READY=0x1; Address(0xf0[7:0])


SPIPoll 00f0,0,0,01
SPIWrite 00a3,00,0,7 //MACRO_OPERAND_REG0=0x1; Address(0xa0[7:0],0xa1[7:0],0xa2[7:0],0xa3[7:0],0xa4[7:0])
SPIWrite 00a2,00,0,7
SPIWrite 00a1,00,0,7
SPIWrite 00a0,01,0,7
SPIWrite 0193,8d,0,7 //MACRO_OPCODE=0x8d; Address(0x193[7:0],0x194[7:0])

WAIT 0.001
SPIRead 00f0,2,2

//Read MACRO_DONE=0x1; Address(0xf0[7:2])


SPIPoll 00f0,2,2,04
SPIReadCheck 00f0,3,3,00

The final SPIReadCheck gives an error.  Any idea why MACRO_OPCODE=0x8d would not complete?

If I comment out the two failing SPIReadCheck, the scripts completes, but I see some kind of random misalignment in the lanes, from power cycle to power cycle.  I'm using LMFS=8821 with the TI JESD204C IP.  When transmitting a test complex sine wave, I see two tones of different amplitudes at +/- the expected offset frequency from the NCO frequency.  Occasionally, one of the 4 DACs has a good output (single offset tone), but across power cycles, the bad behavior occurs randomly on different DAC channels.  I am wondering if the failing MACROs could account for this strange behavior.

 

Thanks for any help or suggestions!

  • 0
    TI__Genius 13240 points

    Hi David,

    Just to confirm, it is only the readchecks that are failing and not the SPI poll before the readcheck? If only the readcheck then I would ask that you add the following register reads after the readcheck. These registers are used to readback any information in regards to MACRO errors and if you can provide the values that are read back then we can provide more info on the error your are seeing.

    In addition to the writes I recommend above there are a couple of other things that can be looked at on your board. The first is that MACROs are sensitive to the power rails, can you confirm that all of the rails are within the datasheet ranges? The second is that the the Sysref must be given at the required time during the bringup. Can you confirm that the AFE configuration was generated for a not continuous sysref and that the sysref pulses are given at the times outlined in the bringup file? 

    For the MACRO opcode 0x78, we have seen issues caused by the Burst writes not being implemented or not correctly implemented. Can you confirm that the burst writes are being implemented in your setup? One easy test to verify if the burst writes are working as expected is to use a fixed bus write sequence and read the registers sequentially. An example of this is to do the following burst write, SPIBurstWrite 0010, [01,02,03,04,05,06,07,08,09,0A], then read SPI address from 0x10 to 0x19 and confirm if readout is as expected. Later set all address back to zero.

    Regards,

    David Chaparro 

  • 0
    Prodigy 60 points

    Hi David,

    Thanks for your help.  Yes, I can confirm that burst writes are being used in our setup and that only the ReadCheck, not the Poll, is failing.  Here are the results of the tests you asked for:

    The values of the reads after the MACRO with opcode 0x78 fails are:

    00f0 - 0x4f

    00f1 - 0x78

    00f2- 0x08

    00f3 - 0x00

    00f4 - 0x00

    00f5 - 0x00

    The values of the reads after the MACRO with opcode 0x8d fails are:

    00f0 - 0x1f

    00f1 - 0x8d

    00f2 - 0x01

    00f3 - 0x00

    00f4 - 0x00

    00f5 - 0x00

    Thanks,

    Dave

  • 0
    Prodigy 60 points

    Hi David,

    There was an issue with the burst write implementation.  After fixing that, the two MACROs no longer fail.  Sorry for the false alarm.

    Thanks,

    Dave