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AFE7950: Clarification on SFDR Performance foi Low Amplitude Signals in AFE7950 ADC

Luiz Camargo
Prodigy 30 points
Part Number: AFE7950
Other Parts Discussed in Thread: AFE7906

Tool/software:

I am analyzing the specifications provided in the datasheet for the AFE7950 ADC converter, especially the SFDR values for different amplitudes of the input analog signal. As described, the ADC has an SFDR of:

- -71 dBFS for a -3 dBFS signal (frequency: 9610 MHz)
- -80 dBFS for a -13 dBFS signal (frequency: 9610 MHz)

From observing the graphs, it appears that the SFDR value improves as the amplitude of the input signal decreases, with the best SFDR value of -80 dBFS occurring for an input signal of -13 dBFS. I would like to confirm whether, for signals with amplitudes lower than -13 dBFS, the SFDR tends to become linear and remains close to the optimal value of -80 dBFS, or if there are other characteristics of the ADC's performance that we should consider for these lower amplitude signals.

The reason for this inquiry is the question of what is the smallest signal that the ADC converter can distinguish from noise, spurious, and harmonic distortions. I understand that if there is an SFDR of -80 dBFS, then a -75 dBFS signal would be distinguishable and converted by the ADC.

Thank you for your attention, and I look forward to your response.

Sincerely,
Luiz Gustavo.

  • 0
    TI__Expert 3750 points

    Hi Luiz,

    Like you said, the SFDR value can improve as the amplitude of the signal decreases.

    In the datasheet section 7.12 there are plots for the in band SFDR vs input amplitude like figure 7-344. And there are also FFT plots like figure 7-486 where you can see if there are any in band spurs as they decrease the input amplitude. For this figure as an example, there is only one spur outside the DDC pass band around -85dBFS. But if you do not count that because it is outside the passband, the SFDR would be determined by the noise floor that is about -100dBFS.

    Best,

    Camilo

  • 0 in reply to Camilo Garcia Trujillo
    Prodigy 30 points

    I completely understand, Camilo. However, I still have questions about the minimum amplitude value at the AD analog input that can be distinguished from noise, harmonics, and spurious signals. For instance, if I want to convert a signal centered at 9.45 GHz, what would be the minimum signal amplitude at the AD input?

    Basically, the question is about understanding the dynamic range of the AD converter for each frequency of interest. In our understanding, this could be observed by the SFDR; however, this parameter changes as the amplitude of the input signal varies. For example, would I be able to convert a -90 dBFS signal at the AD input, considering that a -85 dBFS spurious signal is outside the DDC pass band?

  • 0 in reply to Luiz Camargo
    TI__Expert 3750 points

    Hi Luiz,

    As long as you can distinguish your signal from the noise floor or any in band spurs, that would be the lowest signal you can detect. For example, using figure 7-486 you can see that as long as the input is higher than the noise floor around -100dBFS you will be able to tell that is there because it has been captured by the ADC. And you can also reduce the noise floor level until a certain point by taking more samples per capture.

    If this explanation does not make sense, let me know and I will try to explain it in a different way.

    How low of an input are you trying to capture?

    Best,

    Camilo

  • 0 in reply to Camilo Garcia Trujillo
    Prodigy 30 points

    Your explanation makes sense, and I understand it. Although we are not certain about the smallest signal we need to capture, our application requires a total dynamic range of 120 dB.

    Given that our application requires a dynamic range of 120 dB, we have the following questions:

    1. What methods can be employed to reduce the noise floor, assuming the ADC is operating at its maximum sampling rate? Specifically, can decimation be used to reduce the noise floor? If so, what is the relationship between the noise floor reduction and the chosen decimation factor?

    2. For our application, we need to process signals within a dynamic range of 120 dB. Can the AFE7950 or AFE7906 ADC achieve this dynamic range? I assume that the internal DSA allows for a 120 dB dynamic range since signals exceeding the ADC's full scale would be attenuated (up to 25 dB). In other words, if the noise floor is -100 dBFS, does the presence of a 25 dB DSA mean we achieve a 125 dB dynamic range?

    3. What is the full-scale value for the AFE7950 and AFE7906 ADCs?

    It is crucial for our application to achieve a 120 dB dynamic range. Understanding whether the component can meet this requirement will help determine if we need to implement an STC/AGC circuit at the ADC input to enhance the system's dynamic range.

    Best Regards,

    Luiz.

  • +1 in reply to Luiz Camargo
    TI__Expert 3750 points

    Hi Luiz,

    1. What methods can be employed to reduce the noise floor, assuming the ADC is operating at its maximum sampling rate? Specifically, can decimation be used to reduce the noise floor? If so, what is the relationship between the noise floor reduction and the chosen decimation factor?

    To reduce the noise floor of the ADC the common methods that are used would be to either increase the number of points per capture, increase the decimation factor, average captures or combine multiple ADC channels together through summation. For example, if you keep everything the same and double the number of points per capture, you should see close to 3dB lower noise floor in power.

    1. For our application, we need to process signals within a dynamic range of 120dB. Can the AFE7950 or AFE7906 ADC achieve this dynamic range? I assume that the internal DSA allows for a 120 dB dynamic range since signals exceeding the ADC's full scale would be attenuated (up to 25 dB). In other words, if the noise floor is -100 dBFS, does the presence of a 25 dB DSA mean we achieve a 125 dB dynamic range?

    Let me check with our team internally on this, as there might be other things to consider.

    1. What is the full-scale value for the AFE7950 and AFE7906 ADCs?

    The full-scale value is given in the specification section of each datasheet. For AFE7950 is section 7.6 and for AFE7906 is section 6.5.

    Best,

    Camilo

  • 0 in reply to Camilo Garcia Trujillo
    Prodigy 30 points

    Hi Camilo,

    Thank you very much for the answers. I will be waiting for the response to question 02.

    Best Regards,

    Luiz.

  • +1 in reply to Luiz Camargo
    TI__Expert 3750 points

    Hi Luiz,

    In regards to question 2, the answer would be yes, you can achieve a 120dB dynamic range as long as you can lower your noise floor enough through any of the methods I described in the answer to question 1 (Or multiple of of them combined) so that you can distinguish your lowest signal from the noise floor or any spurs.

    The DSA will also increase your dynamic range, however you should keep in mind that regardless of the DSA value, you should not exceed the reliability limit at the device pins. Therefore, the DSA will extend your dynamic range up to the reliability limit.

    Best,

    Camilo