AFE7950EVM: JESD 8-lane configuration, SYNC_N not received

Obul reddy

Prodigy 125 points

Part Number: AFE7950EVM

Tool/software:

Hi,

I am using AFE7950EVM along with microchip MPF300EVM.

with 2 lanes configuration, I am able to make the JESD link up and test the waveform also.

Now I am trying with 8-lanes.

Inside FPGA, I am getting k28.5 charactors in both directions.

In JESD RX, FPGA is sending sync but the ILA sequence is not received. In JESD TX, The sync is not received by FPGA to send ILA sequence.

I am using single ended SYNC signal adc_sync0, dac_sync0

The latte script used is attached below. Please help me with the debugging

Fullscreen 5037.latte_script.txt Download

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##############      Read me         ##############
#In HSDC Pro DAC tab, Select AFE79xx_2x2TX_44210; Data Rate = 245.76M
#In HSDC Pro ADC tab, Select AFE79xx_2x2RX_44210; Data Rate = 245.76M ---> To capture 4 RX channels
sysParams=AFE.systemParams
sysParams.__init__();sysParams.chipVersion=chipVersion
setupParams.skipFpga = 1 # setup FPGA (TSW14J56) using HSDC Pro 
##############      Top Level           ##############
sysParams.FRef          = 491.52
sysParams.FadcRx        = 2949.12
sysParams.FadcFb        = 2949.12
sysParams.Fdac          = 2949.12*4
sysParams.externalClockRx=False
sysParams.externalClockTx=False
                                                    
##############      Digital Chain       ##############
        #####   RX  #####
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

##############		Read me			##############
#In HSDC Pro DAC tab, Select AFE79xx_2x2TX_44210; Data Rate = 245.76M
#In HSDC Pro ADC tab, Select AFE79xx_2x2RX_44210; Data Rate = 245.76M ---> To capture 4 RX channels

sysParams=AFE.systemParams
sysParams.__init__();sysParams.chipVersion=chipVersion

setupParams.skipFpga = 1 # setup FPGA (TSW14J56) using HSDC Pro 
##############		Top Level			##############
sysParams.FRef			= 491.52
sysParams.FadcRx		= 2949.12
sysParams.FadcFb		= 2949.12
sysParams.Fdac			= 2949.12*4
sysParams.externalClockRx=False
sysParams.externalClockTx=False
													
##############		Digital Chain		##############

		#####	RX	#####
sysParams.ddcFactorRx	=	[12,12,12,12]			#DDC decimation factor for RX A, B, C and D
sysParams.rxNco0		= 	[[9500,9500],			#Band0, Band1 for RXA 
							[9500,9500],        	#Band0, Band1 for RXB 
							[9500,9500],        	#Band0, Band1 for RXC 
							[9500,9500]]        	#Band0, Band1 for RXD  

		#####	FB	#####
sysParams.fbEnable		=	[False,False]
sysParams.ddcFactorFb	=	[12,12]					#DDC decimation factor for FB 1 and 2
sysParams.fbNco0		= 	[9500,9500]				#Band0 for FB1 and FB2 

		#####	TX	#####
sysParams.ducFactorTx	=	[48,48,48,48]			#DUC interpolation factor for TX A, B, C and D
sysParams.txNco0		= 	[[9500,9500],			#Band0, Band1 for TXA 
							[9500,9500],        	#Band0, Band1 for TXB 
							[9500,9500],        	#Band0, Band1 for TXC 
							[9500,9500]]        	#Band0, Band1 for TXD


##############		JESD		##############

		#####	ADC-JESD	#####
sysParams.jesdSystemMode= [3,3]
													#SystemMode 0:	2R1F-FDD						; rx1-rx2-fb -fb
													#SystemMode 1:	1R1F-FDD						; rx -rx -fb -fb
													#SystemMode 2:	2R-FDD							; rx1-rx1-rx2-rx2
													#SystemMode 3:	1R								; rx -rx -rx -rx
													#SystemMode 4:	1F								; fb -fb- fb -fb
													#SystemMode 5:	1R1F-TDD						; rx/fb-rx/fb-rx/fb-rx/fb
													
sysParams.jesdTxProtocol= [0,0]						# 0 - 8b/10b encoding; 2 - 64b/66b encoding 
sysParams.LMFSHdRx		= ["44210","44210","44210","44210"]
													# The 2nd and 4th are valid only for jesdSystemMode values in (0,2).
													# For other modes, select 4 converter modes for 1st and 3rd.
sysParams.LMFSHdFb		= ["22210","22210"]

sysParams.rxJesdTxScr	= [False,False,False,False]
sysParams.fbJesdTxScr	= [False,False]

sysParams.rxJesdTxK		= [16,16,16,16]
sysParams.fbJesdTxK		= [16,16]

sysParams.jesdTxLaneMux	= [0,1,2,3,4,5,6,7]			# Enter which lanes you want in each location. 
													# For example, if you want to exchange the first two lines of each 2T,
													#		this should be [[1,0,2,3],[5,4,6,7]]

		#####	DAC-JESD	#####
sysParams.jesdRxProtocol= [0,0]
sysParams.LMFSHdTx		= ["44210","44210","44210","44210"]
sysParams.jesdRxLaneMux	= [0,1,2,3,4,5,6,7]			# Enter which lanes you want in each location.
													# For example, if you want to exchange the first two lines of each 2R
													#		this should be [[1,0,2,3],[5,4,6,7]]
sysParams.serdesRxLanePolarity = [1,1,1,1,0,0,0,0]
sysParams.jesdRxRbd		= [4, 4]
sysParams.jesdRxScr		= [False,False,False,False]
sysParams.jesdRxK		= [16,16,16,16]

		#####	JESD Common	#####
	
sysParams.jesdABLvdsSync= False
sysParams.jesdCDLvdsSync= False
sysParams.syncLoopBack	= True	#JESD Sync signal is connected to FPGA

##############		GPIO		##############
sysParams.gpioMapping	= {
						'H8': 'ADC_SYNC0',
						'H7': 'ADC_SYNC1',
						'N8': 'ADC_SYNC2',
						'N7': 'ADC_SYNC3',
						'H9': 'DAC_SYNC0',
						'G9': 'DAC_SYNC1',
						'N9': 'DAC_SYNC2',
						'P9': 'DAC_SYNC3',
						'P14': 'GLOBAL_PDN',
						'K14': 'FBABTDD',
						'R6': 'FBCDTDD',
						'H15': ['TXATDD','TXBTDD'],
						'V5': ['TXCTDD','TXDTDD'],
						'E7': ['RXATDD','RXBTDD'],
						'R15': ['RXCTDD','RXDTDD']}

##############		LMK Params		##############
lmkParams.pllEn			= True
lmkParams.inputClk		= 983.04 # Valid only when lmkParams.pllEn = False
lmkParams.lmkFrefClk	= True
setupParams.fpgaRefClk	= 122.88 # Should be equal to LaneRate/40 for TSW14J56

##############		Logging		##############
logDumpInst.setFileName(ASTERIX_DIR+DEVICES_DIR+r"\Afe79xxPg1.txt")
logDumpInst.logFormat=0x0 #Modify to 0x1 to save register scequence to log file. Script takes more time to execute.
logDumpInst.rewriteFile=1
logDumpInst.rewriteFileFormat4=1
device.optimizeWrites=0
device.rawWriteLogEn=1

device.delay_time = 0
#-------------------------------------------------------------------------------------------------#
AFE.deviceBringup()
lmk.head.page.DCLK8_SDCLK9_controls.Clkout_pdn_dis.sdclk_pdn=0
lmk.head.page.DCLK8_SDCLK9_controls.Out_control.dclkout_DIV_lt_4_0_gt=24
lmk.head.page.DCLK8_SDCLK9_controls.Clkout_pdn_dis.pdn_dclk_sdclk=0
AFE.saveCAfeParamsFile()
AFE.TOP.overrideTdd(15,3,15)	# bit-wise; 4R,2F,4T

8 months ago

0 Obul reddy 8 months ago

Prodigy 125 points

one more info:

I gave 'AFE.adcDacSync()' command in latte and the following log is displayed

###########Device DAC JESD-RX 0 Link Status###########
CS State TX0: 0b10101010 . It is expected to be 0b10101010
FS State TX0: 0b01010101 . It is expected to be 0b01010101
Could get the link up for device RX: 0
###################################
###########Device DAC JESD-RX 1 Link Status###########
CS State TX0: 0b10101010 . It is expected to be 0b10101010
FS State TX0: 0b01010101 . It is expected to be 0b01010101
Could get the link up for device RX: 1
###################################
#======

still could not see the sync signals at FPGA

0 David Chaparro 8 months ago in reply to Obul reddy

TI__Genius 17831 points

Hi Obul,

Before performing the 'AFE.adcDacSync()' are there any errors? The log you are showing indicates that the link is up so the sync signal should be seen on the FPGA side.

If you probe the sync signal, do you see it go low during the link-up then back high?

Regards,

David Chaparro

RF & microwave

RF & microwave forum

AFE7950EVM: JESD 8-lane configuration, SYNC_N not received