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TRF3722: TRF3722 PLL unlock issue in low temp

Part Number: TRF3722

Hello Team,

Currently my customer found that some TRF3722 will be unlock in low temp.Could you please help to give some advice to debug this issue? Thank you very much!

Device config: ref input is 10M. PLL config to be 950M to 1700M.

When does the issue come: When the temp decrease to be -30degC.

Tests we did and will do:

1. Do VCO calibration when issue comes in low temp, when the VCO is configured to be certain frequency, the PLL can lock. But for certain frequencies, the PLL can't lock after do calibration.

2. We tried the same test around the bad freq (the PLL freq that PLL can't lock even after calibration). When the freq offset from the bad freq is smaller than +/-500kHz, issue exists. When the freq offset from the bad freq is larger than +/-500kHz, issue may go away. Since the issue comes at certain frequency, i'm suspecting that some cap in the VCO capacitor matix maybe bad.

3. We are also going to decrease the v_cal_ref voltage (bit23,24,25 of register 0xd) to see if the issue can go away. For the current config with issue, it's set to be 1.11V, and we are going to try 0.9V.

  • Hi,

    Could you please try to slow down the Cal clock (increase divider ratio) to check to stability of the lock?

  • Hi Kang,

    Do you mean that slow down the cal_clk by 0x9's bit27-30 and check the lock stability in low temp? The current config is [1111]=fastest(Rdiv/128) and I will try [1000]=default(1xRdiv). May I ask you why you are suspecting the CAL_CLK will trigger this issue? Thanks.

  • Hi Qiang,

    you may refer to section 8.4.4. The cal process compares a PTAT (voltage reference that scales with temperature) vs. VCO. By slowing down the cal process, I hope this can help with the settling time of the cal process and therefore be able to further optimize the VCO bank selection.

    We have seen this helping some customers with the temperature stability. 

    -Kang