AFE7070: AFE7070: IO characteristics

Marcus Mueller41

Prodigy 30 points

Part Number: AFE7070

While designing a board for the AFE7070, I came across multiple issues:

Does the LVDS_P/_N output, if unused, need to be terminated?
If LVDS output isn't used at all, does LVDSVDD18 need to be
- connected to 1.8 V?
- decoupled separately?
The maximum currents
- I_IOVDD,
- I_CLKVDD18,
- I_DACVDD18,
- I_LVDSVDD18 and
- I_DACVDD33
  are inconveniently unspecified in the datasheet table on p.5.
  Can a maximum supply current for these be clarified?
  This is kind of central to power supply design in low-power mass application.
In Dual Input Clock Mode, it seems that DACCLK_P and CLK_IO can be identical, in which case the data lines should be changed and finished changing in the negative period of DACCLK_P=CLK_IO. Is that correct?
Optional: Does the RFOUT pin withstand operation without load (i.e. with an impedance mismatch -> infinity)?
Optimally: Is there a mode which allows an RF signal path test during manufacturing, and if so, how to access it and what LO/clock would have to be supplied?

Thank you in advance,

Marcus Müller

over 5 years ago

0 Marcus Mueller41 over 5 years ago

Prodigy 30 points

* Is the exposed thermal pad to be connected to GND?

0 jim s over 5 years ago in reply to Marcus Mueller41

TI__Guru* 91947 points

Marcus,

This post has been assigned to the responsible engineer and he will be getting back to you soon.

Regards,

Jim

0 Neeraj Gill over 5 years ago in reply to jim s

TI__Mastermind 20541 points

Hi Marcus,

The LVDS output can be powered down by setting the bit 7 of register address 0x06 to 1. You can leave LVDS output pin unconnected when in power down.

LVDSVDD18 need to be connected to 1.8V.

Yes the exposed thermal pad should be connected to GND.

As shown in figure below in dual clock input mode the CLK_IO need to meet setup and hold time with DATA. Also The DAC clock and data clock must be frequency locked, and a FIFO is used internally to absorb the phase difference between the two clock domains. The phase relationship of CLK_IO and DACCLK can be any phase at the initial sync of the FIFO, and thereafter can move up to ±4 clock cycles before the FIFO input and output pointers overrun and cause data errors.

Regards,

Neeraj

0 Marcus Mueller41 over 5 years ago in reply to Neeraj Gill

Prodigy 30 points

Thank you! The information was worked into the board design.

RF & microwave

RF & microwave forum

AFE7070: AFE7070: IO characteristics