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Original question:

LM26LV: How can I identify the temperature range (or Gain ) of the device?

LM26LV: Thermal pad dielectric

Jim Pitman
Intellectual 390 points
Part Number: LM26LV

I'm designing a discrete 24volt high side switch circuit with Safe Operating Area (SOA) protection and fast current limit protection. The circuit uses a low RDS-on P-channel mosfet in a current limit configuration. That is, a sense resistor is in series with the source of the mosfet that will develop a voltage proportional to the load current coming out of the drain. This voltage is used to regulate the maximum current that will be delivered by the mosfet. I have set this current at 1amp. Less than one amp, the mosfet is saturated fully on, and drops very little V from source to drain so therefore dissipates very little wattage. If the load were to draw more than 1 amp then the mosfet begins to turn off and the voltage across at the drain will regulate to whatever value dependent on the resistance of the load so that only 1 amp is delivered. Worse case is a total load short, 0 ohms. Under this condition, the V across the mosfet is 24v and the current through it is 1amp - 24watts wow! It will heat up... 

I will couple the thermal pad of the mosfet to thermal pad of the LM26L temperature sensor. Should the temperature reach the set point the LM26L will turn off the mosfet. If the short remains, the mosfet it will cylce between the set point and the hysteresis (turn back off) of the LM26L. This cycling is OK because this average temperature is below the SOA limit.

My question: Is it ok to couple the thermal pad of the LM26L via a copper pour to the mosfet drain thermal pad (soldered)? The mosfet drain will be wonder around 24volts - 0.65 volts max under typical load. Hopefully, the dielectric insulation between the LM26L thermal pad and its' other pins is up for the task.

  • 0
    TI__Genius 9310 points

    Jim,

      I looked at the original design files for more information. What I found is that the die silicon oxide is sitting directly on top of the thermal pad. This provides the best thermal sensitivity and thermal conductance possible. The die is not connected electrically to the thermal pad. However: There is no isolation barrier between the thermal pad and the die. No testing was performed for an isolation breakdown voltage. The data sheet does not reflect any information about floating the thermal pad above MAX VDD. That means that the thermal pad is subject to the same restrictions as the die itself. The thermal pad would be restricted to MAX 6VDC as is the rest of the silicon from TI's point of view.