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AWR1642: Register definition in ptrSOCDriverMCB->ptrTopRCMRegs->SPARE1

Part Number: AWR1642

Hi champion,
   In function 'SOC_setMSSLinkState', I find it operate register SPARE1, but I could not find this register definition in TRM.  Could you help to give this information?

Thanks,
Adam

int32_t SOC_setMSSLinkState(SOC_Handle handle, uint8_t state, int32_t* errCode)
{
    SOC_DriverMCB*      ptrSOCDriverMCB;
    int32_t             retVal = 0;

    /* Get the pointer to the SOC Driver Block: */
    ptrSOCDriverMCB = (SOC_DriverMCB*)handle;
    if (ptrSOCDriverMCB == NULL)
    {
        *errCode = SOC_EINVAL;
        retVal   = MINUS_ONE;
    }
    else
    {
        /* Set the operational status for the MSS */
        ptrSOCDriverMCB->ptrTopRCMRegs->SPARE1 = CSL_FINSR (ptrSOCDriverMCB->ptrTopRCMRegs->SPARE1,
                                                            18U,
                                                            18U,
                                                            (uint32_t)state);
    }
    return retVal;
}

  • Hello Adam,
    This is SPARE register and depends on the application how it uses it, due to that it's not explained in TRM.

    In SDK it uses SPARE1 to store MSS/DSS application's bootup status to finally synchronized with other core under mmWave library.


    Regards,
    Jitendra