AWR1243: SPI MISO multiplexing in cascaded design

Igor Frol

Part Number: AWR1243

Hi!
We are designing cascaded radar with 4 AWR1243P.
My question is about SPI MOSI output of AWR1243P. We want to use multislave SPI bus for this design like scheme below.

We want to multiplex MISO line by 4 AWR1243P.
It is specified in datasheet that MISO has pull up.
But what is the state of the MISO of AWR1243P when CS of High (chip unselect)? If state is low communication will fail.
Can this state be controlled? Or we need to use separated SPI buses?

over 5 years ago

0 Cesar over 5 years ago

TI__Guru*** 139099 points

Hi

I have contacted the hw cascade team to answer this question

Thank you
Cesar

0 Randy Rosales over 5 years ago in reply to Cesar

TI__Genius 17680 points

Hi Igor,

The default SPI pull resistor state does not change based on chip-select state. So MISO would still have a weak pull-up applied by the device during SPI transfers. The internal pull resistors will be close to 100kohm. This should enable the line to be driven to whatever state the selected device need to drive it to. I don't see a problem there.

However, for cascaded operation, if your application requires frequent reprogramming of the profile, chirp or frame configuration, I would suggest designing with dedicated SPI masters for each AWR device to help reduce SPI command latency bottlenecks.

Thank you,
-Randy

0 Igor Frol over 5 years ago in reply to Randy Rosales

Prodigy 70 points

Thank you
I was just confused by the low state of MISO in the time chart of Radar Interface Control Document.

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AWR1243: SPI MISO multiplexing in cascaded design