TMP461-SP: TMP461-SP SMBus Timing

Hi Gregory,

Gregory Duperon said:

From page 6 of the datasheet, the data setup (t(HDDAT)) and hold time (t(SUDAT)) is defined for writes on the SMBus. I need to know what the setup and hold time will be for the read cycle of the TMP461-SP device. I would expect the read setup time to be expressed in terms of the rising edge of SCL to data valid. The hold time should be expressed in terms of falling edge of SCL to data invalid. Or something along those lines

The setup and hold time requirements will be the same regardless of whether a TMP461 or the SMBus controller is communicating on the bus. 

Gregory Duperon said:

The data hold time (t(SUDAT)) has a min of 0ns and a max of 900ns for fast mode. What does this really mean? Typically, the minimum is used to express the minimum time the data needs to remain valid after the rising (or falling) edge of a clock. A min of 0ns implies there is no explicit hold time. The max time is a bit confusing.

The maximum hold time is the longest time period you would want to hold data after falling edge of the SCL clock. This is determined by the max data valid time tVD;DAT, and the setup time, and is pulled directly from the I2C standard for fast mode. So if you were operating at 100kHz instead, this hold time max would be 3.45us.

Gregory Duperon said:

I am assuming Figure 1 represents a write cycle to the TMP461 device?

Figure 1 is just a representative image to show how we are defining these timing parameters, it could be a write or read to the TMP461.

Best Regards,
Brandon Fisher