UCC24612: About basic operation

Hirotsugu Kobayashi

Mastermind 9530 points

Part Number: UCC24612

Tool/software:

Hi team,

I have two questions,

1.I have illustrated the transition of the proportional gate drive inhibition period. Is this understanding correct?

2,I have illustrated the timing of changes in the VTHREG threshold. Is this understanding correct?

Although the waveforms differ from the actual operating waveforms, I would like to confirm this as IC operation.

over 1 year ago

0 Mike O' over 1 year ago

TI__Guru* 85716 points

Hello,

Your inquiry is under review and I will get back to you shortly.

Regards,

0 Mike O' over 1 year ago in reply to Mike O'

TI__Guru* 85716 points

Hello,

The UCC24612 controls gate drive based on the level of Vds. Please refer to the figure below.

When V_DS voltage goes negative below V_THVGON the FET turns on. V_THVGON= -240 mV typical
The FET gate drive will stay on as long as V_DS < V_THVGOff = typical -9 mV
When the FET V_DS < V_THREG ( -50 mV) the gate voltage will be at its maximum value ( 8.55 to 10.26 V)
When V_DS reaches V_THREG the gate drive will adjust V_Gto adjust the FET impedance to ensure Ids*Rds = -50 mV
Eventually Ids*Rdson > V_THVGOFF and the gate drive will go low.

Regards,

0 Hirotsugu Kobayashi over 1 year ago in reply to Mike O'

Mastermind 9530 points

Hi Mike,

My question is about the inhibit period transition of proportional gate drive.

The proportional gate drive starts the second half of the drive pulse determined by the previous pulse width.

Does the inhibit period transition as shown in the diagram?

Similarly, does the VTHREG level change as shown in the diagram?

0 Mike O' over 1 year ago in reply to Hirotsugu Kobayashi

TI__Guru* 85716 points

Hello,

Your inquiry is under review and I will get back to you shortly.

Regards,

0 Mike O' over 1 year ago in reply to Mike O'

TI__Guru* 85716 points

Hello,

1. The middle waveform you have should not occur in a flyback. Vout/Vin = (Ns/Np)*D/(1-D)

2. This feature was added to force progressive FET turnoff for designs where Ids*Rds is always greater than 50 mV in CCM designs.

The waveform that you drew below is not correct.

The following information describes how this feature works.

Regards,

0 Hirotsugu Kobayashi over 1 year ago in reply to Mike O'

Mastermind 9530 points

Hi Mike,

My diagrams differ from the actual operating waveforms.

Is the inhibition period of proportional gate control always 50% of the previous cycle?
Does the change in VTHREG level occur when it exceeds 90% of the previous cycle but does not reach -50mV?

0 Mike O' over 1 year ago in reply to Hirotsugu Kobayashi

TI__Guru* 85716 points

Hello,

Your inquiry is under review and I will get back to you shortly.

Regards,

0 Mike O' over 1 year ago in reply to Mike O'

TI__Guru* 85716 points

Hello,

Can you share the waveforms you are seeing? You will need Vd and Vs across the UCC24612, Vg and VDD of the device.

Regards,

Site support

Site support forum

UCC24612: About basic operation