Compiler/TM4C123GH6PM: Assembly language Programming

Prashant Bartakke

Part Number: TM4C123GH6PM

Tool/software: TI C/C++ Compiler

I would like to understand the instructions of ARM Cortex M4 processor core. Hence, I decided to write assembly language program in CCS and execute it instruction by instruction. The code is copy pasted below.

      .global main, var1
   .ref arr

   .thumb       ; use thumb, UAL syntax
   .text
     ; set memory location to flash
main:
   b Ldr_ex
Mov_ex:
   mov R0, #23h
   movs R1, R0       ; APSR (Z flag) affected due to s suffix
   mov R0, #0
   mrs R1, apsr   ; read apsr
   movs R2, #0
   ;mov r4, #1234
   movw R6, #1234h   ;way to load 32 bit value in a register
   movt R6, #8765h
   mvn R2, R1
   vmov S0, r7       ; Floating point instructions Project propoerties
                   ; Compiler optons->processor option-> FP support
   ;ldr r0, var1   ; Observe the encoding of this instruction
   movw R0, #0
   movt R0, #2000h
   ldr R1, [R0]
   movt R1, #00   ; Enable FPU: 0f0h, Disable FPU: 00h
   str R1, [R0]
   vmov S0, R1
   vmov.f32 S1, #1.0
here_m:
   b    here_m

Ldr_ex:
   ;ldr r0, var1   ; Load address of label cpacr in R0
   movw r0, #0
   movt r0, #2000h
   ldr R1,[R0, #04h]       ; Immediate offset
   ldr R2,[R0, #08h]!       ; Immediate offset with writeback

   ;adr r0, var1           ; Restore R0
   movw r0, #0
   movt r0, #2000h
   vldr.32 s3, [r0, #0ch]   ; Loading floating point register

   mov r2, #01
   ldr r3, [r0, r2]   ; register Offset
   str   r0, [r0, r2, LSL #3] ;scaled register offset

   ldr r4, [r0], #04   ;post-index addressing mode

   movw r0, #0           ; load and store multiple
   movt r0, #2000h
   ldmia r0, {r1-r4}

   movw r0, #20h
   movt r0, #2000h
   stmdb r0!, {r1-r4}

   vldmia.64 r0, {D0-D1}

   movw r1, 8000h
   movt r1, 2000h
   msr msp, r1

here_l:
   b    here_l

   .data
Var1:
   .word 0E000ED88h, 01h, 02h, 03h, 04h, 05h, 06h, 07h
   ;put your variables here

   .end

I am facing problems as given below:

1) I am unable to access labels defined in data section from code section. Compiler gives error as label not defined in current section

2) As the assembly code length got increased, compiler is giving following error message, highlighted in boldface letters. The statement at line no. 72 is '.end'

**** Build of configuration Debug for project inst ****

/home/coe/ti/ccs910/ccs/utils/bin/gmake -k -j 4 all -O

Building file: "../main.asm"
Invoking: ARM Compiler
"/home/coe/ti/ccs910/ccs/tools/compiler/ti-cgt-arm_18.12.3.LTS/bin/armcl" -mv7M4 --code_state=16 --float_support=FPv4SPD16 -me --include_path="/home/coe/workspace_v8/inst" --include_path="/home/coe/ti/ccs910/ccs/tools/compiler/ti-cgt-arm_18.12.3.LTS/include" --define=ccs="ccs" --define=PART_TM4C123GH6PM -g --gcc --diag_warning=225 --diag_wrap=off --display_error_number --abi=eabi --preproc_with_compile --preproc_dependency="main.d_raw" "../main.asm"

>> Compilation failure
subdir_rules.mk:7: recipe for target 'main.obj' failed
"../main.asm", INTERNAL ERROR! at line 72: failed to locate symbol for relocation entry at offset 0x00000080 in section ".text"
(null)

This may be a serious problem. Please contact customer support with a
description of the problem and a sample of the sourcefile that caused this
message to appear.
gmake: *** [main.obj] Error 1
gmake: Target 'all' not remade because of errors.

**** Build Finished ****

Reuested to look into the above mentioned list of problems and resolve.

over 4 years ago

0 Prashant Bartakke over 4 years ago

Prodigy 50 points

The '#' symbol is missing in the following instructions indicating that it is immediate operand. I have modified the code and now the error in 2nd point of problems raised in the post is solved. But the problem of label not defined in the same section still persist.

The following pair of instructions :

movw r1, 8000h
movt r1, 2000h

should have been...

movw r1, #8000h
movt r1, #2000h

waiting for the solution..

0 George Mock over 4 years ago in reply to Prashant Bartakke

TI__Guru**** 233150 points

Thank you for reporting this problem. With regard to the problem of the assembler issuing the INTERNAL ERROR diagnostic, I filed the entry CODEGEN-6710 in the SDOWP system to have this investigated. You are welcome to follow it with the SDOWP link below in my signature.

With regard to this problem ...

Prashant Bartakke5 said:
the problem of label not defined in the same section still persist.

I cannot reproduce it. Please prepare an assembly file that demonstrates this problem. Attach to your next post. So the forum will accept it, add the file extension .txt to it. I presume you build it with the options shown in the first post. And you use compiler tools version 18.12.3.LTS.

Thanks and regards,

-George

0 Prashant Bartakke over 4 years ago in reply to George Mock

Prodigy 50 points

As per your suggestion, I have attached main.asm file which is saved as main.txt. Also, the lst file is attached for additional information which contains the error I mentioned in the post i.e. label is not defined in current section.

1526.main.txt

	.global main

	.data
Var1:
	.word 0E000ED88h, 01h, 02h, 03h, 04h, 05h, 06h, 07h
	;put your variables here

	.thumb	   ; use thumb, UAL syntax

	.text
     ; set memory location to flash
main:
	b Ldr_ex
Mov_ex:
	mov R0, #23h
	movs R1, R0		; APSR (Z flag) affected due to s suffix
	mov R0, #0
	mrs R1, apsr	; read apsr
	movs R2, #0
	;mov r4, #1234
	movw R6, #1234h	 ;way to load 32 bit value in a register
	movt R6, #8765h
	mvn R2, R1
	vmov S0, r7		; Floating point instructions Project propoerties
					; Compiler optons->processor option-> FP support
	;ldr r0, var1	; Observe the encoding of this instruction
	movw R0, #0
	movt R0, #2000h
	ldr R1, [R0]
	movt R1, #00	; Enable FPU: 0f0h, Disable FPU: 00h
	str R1, [R0]
	vmov S0, R1
	vmov.f32 S1, #1.0
here_m:
	b 	here_m

Ldr_ex:
	ldr r0, Var1	; Load address of label cpacr in R0
	movw r0, #0
	movt r0, #2000h
	ldr R1,[R0, #04h]		; Immediate offset
	ldr R2,[R0, #08h]!		; Immediate offset with writeback
	strb r2, [r0, #13h]

	adr r0, Var1			; Restore R0
	movw r0, #0
	movt r0, #2000h
	vldr.32 s3, [r0, #0ch]	; Loading floating point register

	mov r2, #01
	ldr r3, [r0, r2]	; register Offset
	str	r0, [r0, r2, LSL #3] ;scaled register offset

	ldr r4, [r0], #04	;post-index addressing mode

	movw r0, #0			; load and store multiple
	movt r0, #2000h
	ldmia r0, {r1-r4}

	movw r0, #20h
	movt r0, #2000h
	stmdb r0!, {r1-r4}

	vldmia.64 r0, {D0-D1}

	movw r1, #8000h
	movt r1, #2000h
	msr msp, r1

here_l:
	b 	here_l

	.end

main_lst.txt

TI ARM Assembler Unix v18.12.3 Mon Sep 30 16:39:01 2019

Copyright (c) 1996-2018 Texas Instruments Incorporated
../main.asm                                                          PAGE    1

       1                            .global main
       2                    
       3 00000000                   .data
       4 00000000           Var1:
       5 00000000 E000ED88          .word 0E000ED88h, 01h, 02h, 03h, 04h, 05h, 06h, 07h
         00000004 00000001 
         00000008 00000002 
         0000000c 00000003 
         00000010 00000004 
         00000014 00000005 
         00000018 00000006 
         0000001c 00000007 
       6                            ;put your variables here
       7                    
       8 00000020                   .thumb     ; use thumb, UAL syntax
       9                    
      10 00000000                   .text
      11                         ; set memory location to flash
      12 00000000           main:
      13 00000000 E01C              b Ldr_ex ; [ORIG 16-BIT INS]
      14 00000002           Mov_ex:
      15 00000002 0023F04F          mov R0, #23h ; [KEEP 32-BIT INS]
      16 00000006 1C01              movs R1, R0             ; APSR (Z flag) affected due to s suffix ; [ORIG 16-BIT INS]
      17 00000008 0000F04F          mov R0, #0 ; [KEEP 32-BIT INS]
      18 0000000c 8100F3EF          mrs R1, apsr    ; read apsr ; [KEEP 32-BIT INS]
      19 00000010 2200              movs R2, #0 ; [ORIG 16-BIT INS]
      20                            ;mov r4, #1234
      21 00000012 2634F241          movw R6, #1234h  ;way to load 32 bit value in a register ; [KEEP 32-BIT INS]
      22 00000016 7665F2C8          movt R6, #8765h ; [KEEP 32-BIT INS]
      23 0000001a 0201EA6F          mvn R2, R1 ; [KEEP 32-BIT INS]
      24 0000001e 7A10EE00          vmov S0, r7             ; Floating point instructions Project propoerties ; [KEEP 32-BIT INS]
      25                                                            ; Compiler optons->processor option-> FP support
      26                            ;ldr r0, var1   ; Observe the encoding of this instruction
      27 00000022 0000F240          movw R0, #0 ; [KEEP 32-BIT INS]
      28 00000026 0000F2C2          movt R0, #2000h ; [KEEP 32-BIT INS]
      29 0000002a 6801              ldr R1, [R0] ; [ORIG 16-BIT INS]
      30 0000002c 0100F2C0          movt R1, #00    ; Enable FPU: 0f0h, Disable FPU: 00h ; [KEEP 32-BIT INS]
      31 00000030 6001              str R1, [R0] ; [ORIG 16-BIT INS]
      32 00000032 1A10EE00          vmov S0, R1 ; [KEEP 32-BIT INS]
      33 00000036 0A00EEF7          vmov.f32 S1, #1.0 ; [KEEP 32-BIT INS]
      34 0000003a           here_m:
      35 0000003a E7FE              b       here_m ; [ORIG 16-BIT INS]
      36                    
      37 0000003c           Ldr_ex:
      38 0000003c 0000F85F          ldr r0, Var1    ; Load address of label cpacr in R0 ; [KEEP 32-BIT INS]
 "../main.asm", ERROR!   at line 38: [E0001] Address must be defined in the current section
 "../main.asm", ERROR!   at line 38: [E0004] Illegal operand
      39 00000040 0000F240          movw r0, #0 ; [KEEP 32-BIT INS]
      40 00000044 0000F2C2          movt r0, #2000h ; [KEEP 32-BIT INS]
      41 00000048 6841              ldr R1,[R0, #04h]               ; Immediate offset ; [ORIG 16-BIT INS]
      42 0000004a 2F08F850          ldr R2,[R0, #08h]!              ; Immediate offset with writeback ; [KEEP 32-BIT INS]
      43 0000004e 74C2              strb r2, [r0, #13h] ; [ORIG 16-BIT INS]
      44                    
      45 00000050 0000F2AF          adr r0, Var1                    ; Restore R0 ; [KEEP 32-BIT INS]
 "../main.asm", ERROR!   at line 45: [E0001] Address must be defined in the current section
TI ARM Assembler Unix v18.12.3 Mon Sep 30 16:39:01 2019

Copyright (c) 1996-2018 Texas Instruments Incorporated
../main.asm                                                          PAGE    2

 "../main.asm", ERROR!   at line 45: [E0004] Illegal operand
 "../main.asm", ERROR!   at line 45: [E0001] Address must be defined in the current section
      46 00000054 0000F240          movw r0, #0 ; [KEEP 32-BIT INS]
      47 00000058 0000F2C2          movt r0, #2000h ; [KEEP 32-BIT INS]
      48 0000005c 1A03EDD0          vldr.32 s3, [r0, #0ch]  ; Loading floating point register ; [KEEP 32-BIT INS]
      49                    
      50 00000060 0201F04F          mov r2, #01 ; [KEEP 32-BIT INS]
      51 00000064 5883              ldr r3, [r0, r2]        ; register Offset ; [ORIG 16-BIT INS]
      52 00000066 0032F840          str     r0, [r0, r2, LSL #3] ;scaled register offset ; [KEEP 32-BIT INS]
      53                    
      54 0000006a 4B04F850          ldr r4, [r0], #04       ;post-index addressing mode ; [KEEP 32-BIT INS]
      55                    
      56 0000006e 0000F240          movw r0, #0                     ; load and store multiple ; [KEEP 32-BIT INS]
      57 00000072 0000F2C2          movt r0, #2000h ; [KEEP 32-BIT INS]
      58 00000076 001EE890          ldmia r0, {r1-r4} ; [KEEP 32-BIT INS]
      59                    
      60 0000007a 0020F240          movw r0, #20h ; [KEEP 32-BIT INS]
      61 0000007e 0000F2C2          movt r0, #2000h ; [KEEP 32-BIT INS]
      62 00000082 001EE920          stmdb r0!, {r1-r4} ; [KEEP 32-BIT INS]
      63                    
      64 00000086 0B04EC90          vldmia.64 r0, {D0-D1} ; [KEEP 32-BIT INS]
      65                    
      66 0000008a 0100F248          movw r1, #8000h ; [KEEP 32-BIT INS]
      67 0000008e 0100F2C2          movt r1, #2000h ; [KEEP 32-BIT INS]
      68 00000092 8808F381          msr msp, r1 ; [KEEP 32-BIT INS]
      69                    
      70 00000096           here_l:
      71 00000096 E7FE              b       here_l ; [ORIG 16-BIT INS]
      72                    
      73                            .end

--------------------------
Thumb2 Statistics
--------------------------
Number of Thumb2 ins converted to Thumb = 0 (0%)
Number of Thumb ins in input = 14 (29%)
Number of Thumb2 ins encoded as Thumb2 = 33 (100%)
Number of Thumb2 ins converted to 2 OPND Thumb = 0


5 Assembly Errors, No Assembly Warnings

0 George Mock over 4 years ago in reply to Prashant Bartakke

TI__Guru**** 233150 points

The assembler is correct to emit those diagnostics. You are accessing global data incorrectly.

Please search the ARM compiler manual for the sub-chapter titled Accessing Assembly Language Functions From C/C++. Note how the example assembly code accesses the variable gvar. Your code needs to do something similar.

Thanks and regards,

-George

0 Prashant Bartakke over 4 years ago in reply to George Mock

Prodigy 50 points

Thank you George. It worked.

As I was into assembly language programming, I kept on searching examples/sample codes in ARM Assembly Language Tool User's Guide and didn't look into Compiler User's Guide.

I would like to seek clarification on the solution suggested. Is it similar to LTORG/.pool assembler directives available in Keil MDK-ARM/Gnu Assembler? These tools generate literal pool in accordance with these directives automatically. In case of TI compiler, using '.field', are we creating literal pool ourselves?

The modified working code is inserted below for the reference. Thanks once again.

main_asm.txt

	.global main

	.data
Var1:
	.word 0E000ED88h, 01h, 02h, 03h, 04h, 05h, 06h, 07h
	;put your variables here

	.thumb	   ; use thumb, UAL syntax

	.text
     ; set memory location to flash
main:
	b Ldr_ex
Mov_ex:
	mov R0, #23h
	movs R1, R0		; APSR (Z flag) affected due to s suffix
	mov R0, #0
	mrs R1, apsr	; read apsr
	movs R2, #0
	;mov r4, #1234
	movw R6, #1234h	 ;way to load 32 bit value in a register
	movt R6, #8765h
	mvn R2, R1
	vmov S0, r7		; Floating point instructions Project propoerties
					; Compiler optons->processor option-> FP support
	;ldr r0, var1	; Observe the encoding of this instruction
	movw R0, #0
	movt R0, #2000h
	ldr R1, [R0]
	movt R1, #00	; Enable FPU: 0f0h, Disable FPU: 00h
	str R1, [R0]
	vmov S0, R1
	vmov.f32 S1, #1.0
here_m:
	b 	here_m

Ldr_ex:
	ldr r0, Var1_a	; Load address of label cpacr in R0
	;movw r0, #0
	;movt r0, #2000h
	ldr R1,[R0, #04h]		; Immediate offset
	ldr R2,[R0, #08h]!		; Immediate offset with writeback
	strb r2, [r0, #13h]

	ldr r0, Var1_a			; Restore R0
	;movw r0, #0
	;movt r0, #2000h
	vldr.32 s3, [r0, #0ch]	; Loading floating point register

	mov r2, #01
	ldr r3, [r0, r2]	; register Offset
	str	r0, [r0, r2, LSL #3] ;scaled register offset

	ldr r4, [r0], #04	;post-index addressing mode

	movw r0, #0			; load and store multiple
	movt r0, #2000h
	ldmia r0, {r1-r4}

	movw r0, #20h
	movt r0, #2000h
	stmdb r0!, {r1-r4}

	vldmia.64 r0, {D0-D1}

	movw r1, #8000h
	movt r1, #2000h
	msr msp, r1

here_l:
	b 	here_l

Var1_a .field Var1, 32

	.end

0 George Mock over 4 years ago in reply to Prashant Bartakke

TI__Guru**** 233150 points

Prashant Bartakke5 said:
These tools generate literal pool in accordance with these directives automatically. In case of TI compiler, using '.field', are we creating literal pool ourselves?

I don't know how this works in the Keil and GCC assemblers. But this description sounds correct.

Thanks and regards,

-George

0 Prashant Bartakke over 4 years ago in reply to George Mock

Prodigy 50 points

Thanks and regards.

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Compiler/TM4C123GH6PM: Assembly language Programming