am4377 : Ethercat rx link and phy COL pin

Hello,

On AM437x the E24 pin reset release state is high-impedance with an active PD resistor. Given that the PHY is PU this pin internally, this would cause the pin voltage to resolve to mid-supply. In your case you will need an external resistor to ensure that the pin is strapped the the correct voltage when the PHY latches it.

Hello,
Thanks for your reply, we understand it. We tried to configure pin E24 of the AM4377 as RXLINK, which is an input pin with pull up. We also tried to configure pin E24 as gpio5_13 input with pull up, but with the same result (1 volt at the COL pin during PHY reset). What can be the cause for this behavior? Is there anything we should check or do to overcome this issue?

Hi,

When you say that you are configuring the pin as GPIO input with PU, when are you doing this? At run-time after the SoC has booted?

Runtime , before the call to phy reset

What is the voltage at E24 with the PHY disconnected from the pin? 

Trying to isolate the problem here. Is the SoC doing what you expect it to do when the PHY is not attached?

Ch1 (yellow) is PHY RESETn. Ch2 (green) is E24

Thanks.

In this plot, the SOC is disconnected from the PHY, you've already changed the PADCONFIG as PU+INPUT and you are measuring the SOC itself?