TIDA-00421: ds90ub913 ds90ub914

Hi Brian,

The TIDA-00421 was developed in conjunction with TIDA-00455.  https://www.ti.com/tool/TIDA-00455  The TIDA-00455 is a 4 camera hub, utilizing the DS90UB960 that connected to a TDA2x EVM.  The final configuration of the system was done from the TDA2 SoC on the EVM and at that time, it was supported in the SDK.

The OV10640 configuration files were supplied by OmniVision.  This was loaded into a FLASH associated with the OV490 ISP, but it could also be loaded from your processor via I2C over the SERDES link.  The Design Guide for the TIDA-00455 explains this procedure. https://www.ti.com/lit/pdf/tiducb9

Below is a section of code used to set up the registers in the DS90UB960 and the DS90UB13.  The setup for your DS90UB914 will be very similar.  You will not need any of the page register writes, since the UB914 is a single channel part.  Please note the delay after releasing PDB on the Deserializer before attempting to write.  This allows time for the ADC to read the IDX pin an set the appropriate I2C address.

void init_UB960 (void)

{

                unsigned char readVal;

                P1OUT |= BIT5;                                                                                 //set P1.5 to 1 (I2C_SW_UB960), sets switch in position 2D+/2D-

                P4OUT |= BIT0;                                                                                //set PDB_UB960 to 1  , release RESET UB960

                __delay_cycles(200000);                                                                               //wait 10mS for supervisor delay

                tsc_WriteI2CReg (UB960_i2c_Address, 0x0C, 0xCF);         //Map FPD-Link control channel 0+1 to I2C port 0 and 2+3 to I2C port 1

                tsc_WriteI2CReg (UB960_i2c_Address, 0x1F, 0x05);          //CSI TX frequency 800mbps (400Mbit VCO)

                tsc_WriteI2CReg (UB960_i2c_Address, 0x10, 0x11);         //gpio 0 set to show output value = 0; drive output low

                tsc_WriteI2CReg (UB960_i2c_Address, 0x11, 0x85);         //gpio 1 RX port 1 lock indication

                tsc_WriteI2CReg (UB960_i2c_Address, 0x13, 0x89);         //gpio 3 RX port 3 lock indication

                tsc_WriteI2CReg (UB960_i2c_Address, 0x14, 0x8D);         //gpio 4 RX port 4 lock indication

                tsc_WriteI2CReg (UB960_i2c_Address, 0x19, 0x01);         //FS_HIGH_TIME_1

                tsc_WriteI2CReg (UB960_i2c_Address, 0x1A, 0x15);         //FS_HIGH_TIME_0

                tsc_WriteI2CReg (UB960_i2c_Address, 0x1B, 0x14);         //FS_LOW_TIME_1

                tsc_WriteI2CReg (UB960_i2c_Address, 0x1C, 0x9C);         //FS_LOW_TIME_0

                tsc_WriteI2CReg (UB960_i2c_Address, 0x18, 0x01);         //ENABLE FRAME SYNC

                tsc_WriteI2CReg (UB960_i2c_Address, 0x4C, 0x01);         //Page FPD3 port RX0 registers for R/W

                tsc_WriteI2CReg (UB960_i2c_Address, 0x58, 0x58);         //set backchannel rate to 2.5Mbit / I2C passthrough enabled

                tsc_WriteI2CReg (UB960_i2c_Address, 0x5D, 0x60);         //imager slave ID = 0x60

                tsc_WriteI2CReg (UB960_i2c_Address, 0x65, 0x60);         //imager slave alias = 0x60

                tsc_WriteI2CReg (UB960_i2c_Address, 0x5E, 0x51);          //EEPROM slave ID = 0x51

                tsc_WriteI2CReg (UB960_i2c_Address, 0x66, 0x51);         //EEPROM slave alias, port0

                tsc_WriteI2CReg (UB960_i2c_Address, 0x7C, 0x01);         //set frame valid polarity low for duration of active video

                tsc_WriteI2CReg (UB960_i2c_Address, 0x4C, 0x12);         //Page FPD3 port RX1 registers for R/W

                tsc_WriteI2CReg (UB960_i2c_Address, 0x58, 0x58);         //set backchannel rate to 2.5Mbit / I2C passthrough enabled

                tsc_WriteI2CReg (UB960_i2c_Address, 0x5D, 0x60);         //imager slave ID = 0x60

                tsc_WriteI2CReg (UB960_i2c_Address, 0x65, 0x62);         //imager slave alias = 0x62

                tsc_WriteI2CReg (UB960_i2c_Address, 0x5E, 0x51);          //EEPROM slave ID = 0x51

                tsc_WriteI2CReg (UB960_i2c_Address, 0x66, 0x53);         //EEPROM slave alias, port1

                tsc_WriteI2CReg (UB960_i2c_Address, 0x7C, 0x01);         //set frame valid polarity low for duration of active video

                tsc_WriteI2CReg (UB960_i2c_Address, 0x4C, 0x24);         //Page FPD3 port RX2 registers for R/W

                tsc_WriteI2CReg (UB960_i2c_Address, 0x58, 0x58);         //set backchannel rate to 2.5Mbit / I2C passthrough enabled

                tsc_WriteI2CReg (UB960_i2c_Address, 0x5D, 0x60);         //imager slave ID = 0x60

                tsc_WriteI2CReg (UB960_i2c_Address, 0x65, 0x64);         //imager slave alias = 0x64

                tsc_WriteI2CReg (UB960_i2c_Address, 0x5E, 0x51);          //EEPROM slave ID = 0x51

                tsc_WriteI2CReg (UB960_i2c_Address, 0x66, 0x55);         //EEPROM slave alias, port2

                tsc_WriteI2CReg (UB960_i2c_Address, 0x7C, 0x01);         //set frame valid polarity low for duration of active video

                tsc_WriteI2CReg (UB960_i2c_Address, 0x4C, 0x38);         //Page FPD3 port RX3 registers for R/W

                tsc_WriteI2CReg (UB960_i2c_Address, 0x58, 0x58);         //set backchannel rate to 2.5Mbit / I2C passthrough enabled

                tsc_WriteI2CReg (UB960_i2c_Address, 0x5D, 0x60);         //imager slave ID = 0x60

                tsc_WriteI2CReg (UB960_i2c_Address, 0x65, 0x66);         //imager slave alias = 0x66

                tsc_WriteI2CReg (UB960_i2c_Address, 0x5E, 0x51);          //EEPROM slave ID = 0x51

                tsc_WriteI2CReg (UB960_i2c_Address, 0x66, 0x57);         //EEPROM slave alias, port3

                tsc_WriteI2CReg (UB960_i2c_Address, 0x7C, 0x01);         //set frame valid polarity low for duration of active video

                tsc_WriteI2CReg (UB960_i2c_Address, 0x4C, 0x0F);          //All ports write enable

                tsc_WriteI2CReg (UB960_i2c_Address, 0x0F, 0x00);          //disable all GPIO inputs

                tsc_WriteI2CReg (UB960_i2c_Address, 0x6E, 0x88);          //set GPIO1 (nRESET) and GPIO0 (FSIN) to 0 for all four cameras

                tsc_WriteI2CReg (UB960_i2c_Address, 0x6f, 0x88);           //set GPIO3          and GPIO2        to 0 for all four cameras

                tsc_WriteI2CReg (UB960_i2c_Address, 0x4C, 0x01);          //Page FPD3 port RX0 registers for R/W

                tsc_WriteI2CReg (UB960_i2c_Address, 0x70, 0x2B);          //RAW10_ID: MSB:00: Assign VC 0 to RX0 CSI data type: (0x2B matches CSI spec)

                tsc_WriteI2CReg (UB960_i2c_Address, 0x71, 0x2C);          //RAW12_ID: MSB:00: Assign VC 0 to RX0 CSI data type: (0x2C matches CSI spec)

                tsc_WriteI2CReg (UB960_i2c_Address, 0x72, 0x00);          //CSI_VC_MAP: remap all input packets from RX0 to VC_ID0

                tsc_WriteI2CReg (UB960_i2c_Address, 0x4C, 0x12);          //Page FPD3 port RX1 registers for R/W

                tsc_WriteI2CReg (UB960_i2c_Address, 0x70, 0x6B);          //RAW10_ID: MSB:01: Assign VC 1 to RX1 CSI data type: (0x2B matches CSI spec)

                tsc_WriteI2CReg (UB960_i2c_Address, 0x71, 0x6C);          //RAW12_ID: MSB:01: Assign VC 1 to RX1 CSI data type: (0x2C matches CSI spec)

                tsc_WriteI2CReg (UB960_i2c_Address, 0x72, 0x01);          //CSI_VC_MAP: remap all input packets from RX1 to VC_ID1

                tsc_WriteI2CReg (UB960_i2c_Address, 0x4C, 0x24);          //Page FPD3 port RX2 registers for R/W

                tsc_WriteI2CReg (UB960_i2c_Address, 0x70, 0x2B);          //RAW10_ID: MSB:00: Assign VC 0 to RX2 CSI data type: (0x2B matches CSI spec)

                tsc_WriteI2CReg (UB960_i2c_Address, 0x71, 0x2C);          //RAW12_ID: MSB:00: Assign VC 0 to RX2 CSI data type: (0x2C matches CSI spec)

                tsc_WriteI2CReg (UB960_i2c_Address, 0x72, 0x00);          //CSI_VC_MAP: remap all input packets from RX2 to VC_ID0

                tsc_WriteI2CReg (UB960_i2c_Address, 0x4C, 0x38);          //Page FPD3 port RX3 registers for R/W

                tsc_WriteI2CReg (UB960_i2c_Address, 0x70, 0x6B);          //RAW10_ID: MSB:01: Assign VC 1 to RX3 CSI data type: (0x2B matches CSI spec)

                tsc_WriteI2CReg (UB960_i2c_Address, 0x71, 0x6C);          //RAW12_ID: MSB:01: Assign VC 1 to RX3 CSI data type: (0x2C matches CSI spec)

                tsc_WriteI2CReg (UB960_i2c_Address, 0x72, 0x01);          //CSI_VC_MAP: remap all input packets from RX3 to VC_ID1

                tsc_WriteI2CReg (UB960_i2c_Address, 0x32, 0x01);         //read from CSI port0, write to CSI port0

                tsc_WriteI2CReg (UB960_i2c_Address, 0x33, 0x01);         //enable CSI port0, 4-lanes, Normal operation

                tsc_WriteI2CReg (UB960_i2c_Address, 0x32, 0x12);         //read from CSI port1, write to CSI port1

                tsc_WriteI2CReg (UB960_i2c_Address, 0x33, 0x01);         //enable CSI port1, 4-lanes, Normal operation

                tsc_WriteI2CReg (UB960_i2c_Address, 0x20, 0x0C);         //VC 0+1 routed to CSI port 0, VC 2+3 routed to CSI port 1

                P1OUT &= ~BIT5;                                                                             //set P1.5 to 0 (I2C_SW_UB960), sets switch in position 1D+/1D-

}

void enable_FSIN(void)

{

                P1OUT |= BIT5;

                tsc_WriteI2CReg (UB960_i2c_Address, 0x4c, 0x01);                          //Page FPD3 port RX0 registers for R/W

                tsc_WriteI2CReg (UB960_i2c_Address, 0x6e, 0x9a);                          //keep GPIO1 of camera 0 to 1; output frame sync on GPIO0

                tsc_WriteI2CReg (UB960_i2c_Address, 0x4c, 0x12);                          //Page FPD3 port RX1 registers for R/W

                tsc_WriteI2CReg (UB960_i2c_Address, 0x6e, 0x9a);                          //keep GPIO1 of camera 0 to 1; output frame sync on GPIO0

                tsc_WriteI2CReg (UB960_i2c_Address, 0x4c, 0x24);                          //Page FPD3 port RX2 registers for R/W

                tsc_WriteI2CReg (UB960_i2c_Address, 0x6e, 0x9a);                          //keep GPIO1 of camera 0 to 1; output frame sync on GPIO0

                tsc_WriteI2CReg (UB960_i2c_Address, 0x4c, 0x38);                          //Page FPD3 port RX3 registers for R/W

                tsc_WriteI2CReg (UB960_i2c_Address, 0x6e, 0x9a);                          //keep GPIO1 of camera 0 to 1; output frame sync on GPIO0

                tsc_WriteI2CReg (UB960_i2c_Address, 0x10, 0x91);         //gpio 0 set to pass generated frame sync signal

                P1OUT &= ~BIT5;

}

Hi Brian,

I think the best practice here is to set the value of the pin with a resistor divider as shown in the data sheet.  You can override this after boot buy changing the register.  

By the way, have you seen the app note about migrating to a newer set of parts?  https://www.ti.com/lit/pdf/snla286

Best Regards,

Brian

Hello Brian,

The DS90UB960-Q1 is compatible with all other FPD-Link III cameras that include DS90UB913A-Q1, DS90UB933-Q1, DS90UB935-Q1 or DS90UB953-Q1 serializers. Deserializers with pixel bus (DVP) interface are considered legacy at this point so we only have DS90UB14A-Q1 or DS90UB934-Q1 deserializers in our portfolio and no plans for next generation deserializers with this interface. Technically it is possible to link those devices with DS90UB935-Q1 or DS90UB953-Q1 as well, but there are specific clocking requirements. You can see info about that here: https://www.ti.com/lit/pdf/snla270#:~:text=The%20DS90UB953%2DQ1%20is%20capable,previous%20generation%20DS90UB914A%2DQ1%20deserializers.

Best Regards,

Casey