TIDA-010062: About PFC Lab 2

SJZ

Part Number: TIDA-010062
Other Parts Discussed in Thread: SFRA,

Hello,

I have cleared Lab1 for the TTPL PFC.

As per the the section (3.1.2.5.2.3) of TIDUET7G, Lab 2 test, the expected result is given as 46V, 0.7Amp at 100 Ohms Load.

However on running the same code without any changes to the same board (just with changed Inductor with inductance value around 500uH at no load)

I am getting around 68V at the output with the following values and the TTPLPFC_DutyPU is also a little higher- 0.419(compared to 0.2625 in the screenshot of document)

Also according to the Boost equation, with 0.2625 duty, the output voltage should be around 40V (not 46V as mentioned in document)

- Why am I getting different Voltage output for Lab 2?

- Does the preloaded / already existing coefficients of Lab 2 Compensation designer are for stable system?

In the Compensation Designer, tool is showing unstable system with already modelled coefficients. I was expecting it to be already stable for this design.

Regards,

10 months ago

0 Desheng, Guo 10 months ago

TI__Expert 6180 points

I am thinking, maybe your MOSFET leg isn't triggerred normally.

0 SJZ 10 months ago in reply to Desheng, Guo

Intellectual 300 points

MOSFET Waveforms looks normal to me

These are the MOSFET Gate waveforms switching at D = 0.42(approx) as monitored real time in the window.

Below are the Gate waveforms of GaN MOS.

And below is the Vds waveform across the lower MOSFET:

MOSFET Waveforms looks normal to me. Can you please elaborate?

Regards,

0 Desheng, Guo 10 months ago in reply to SJZ

TI__Expert 6180 points

I am talking about the low frequency leg, your waveforms are all GaN HEMET switching.

0 SJZ 10 months ago in reply to Desheng, Guo

Intellectual 300 points

May I know what should be the expected waveforms for Low Frequency MOS in Lab 2?

For Low Frequency MOS, Q5 has 3.3V constant voltage at Vgs and Q4 is having Vgs at 0V.

0 Desheng, Guo 10 months ago in reply to SJZ

TI__Expert 6180 points

3.3V is logic PWM, you need 12V on Vgs to open it.

You can check the Vds of Q5, it should be locked on 0V.

0 SJZ 10 months ago in reply to Desheng, Guo

Intellectual 300 points

Check below screenshot 12V observed at Vgs of Q5:

And the Vds at Q5 is also locked at 0V(screenshot below):

Then what is the problem here?

Regards,

0 Desheng, Guo 10 months ago in reply to SJZ

TI__Expert 6180 points

OK, your problem may be else where.

0 SJZ 10 months ago in reply to Desheng, Guo

Intellectual 300 points

The pre- modelled Compensation designer GUI of the PFC Lab 2 is showing the plot as below:

Can you verify if these are the correct values for successfull running of Lab2?

Since Gain Margin and Phase Margin values seems too low.

Regards,

0 SJZ 9 months ago in reply to SJZ

Intellectual 300 points

Hello,

Any updates on this?

0 Desheng, Guo 9 months ago in reply to SJZ

TI__Expert 6180 points

The compensator should be good.

There is a known bug with the SFRA.

Change to be made in “ttplpfc_user_settings.h” file of TIDA-010062 with F28003x

// SFRA related
#define TTPLPFC_SCI_VBUS_CLK 30000000

instead of 50000000{}

0 SJZ 9 months ago in reply to Desheng, Guo

Intellectual 300 points

Hello,

Currently the problem was not related to the connection/bug of SFRA. I already made those changes in the firmware. However, I will try checking the SFRA with this compensator.

Regards,

0 Desheng, Guo 9 months ago in reply to SJZ

TI__Expert 6180 points

OK, let us know your result.

0 SJZ 9 months ago in reply to Desheng, Guo

Intellectual 300 points

Hello,

While Testing Lab 2, the TTPLPFC_guiL_Amps is at 0.7Amps but first the output voltage comes as 66V, then it drops down until the switching stops and restarts again with output voltage again raising upto 66V and then slowly settles near 49V: