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Original question:

LM5118 PSPICE reference simulation not converging

LM5118-Q1: PSpice simulation fails to converge

bseck
Prodigy 40 points
Part Number: LM5118-Q1
Other Parts Discussed in Thread: LM5118, TIDA-01179

Hello,

I'm simulating the buck-boost converter reference design found in TIDA-01179, however the simulation fails with various convergence problems:


WARNING(ORPSIM-16534): Using high values of ITL4 for Speed Level > 0 may increase total simulation job time.
Reducing minimum delta to make the circuit converge.
Reducing minimum delta to make the circuit converge.
Reducing minimum delta to make the circuit converge.
Reducing minimum delta to make the circuit converge.

ERROR(ORPSIM-15138): Convergence problem in Transient Analysis at Time = 124.8E-06.
Time step = 291.0E-21, minimum allowable step size = 1.000E-18

These voltages failed to converge:

V(X_U1.conv3) = 37.65uV \ 4.915uV
V(X_X3.10) = 924.83mV \ 938.30mV
V(X_X3.7) = 924.83mV \ 938.30mV
V(X_X3.4) = 924.83mV \ 938.30mV

These supply currents failed to converge:

I(X_L1.Edc) = 37.75mA \ 37.88mA
I(X_U1.Errout) = 47.20uA \ 47.28uA
I(V_V_Icout1) = -102.05mA \ -101.94mA
I(X_U1.XA_DFF.V2) = -19.09nA \ -1.399nA

These devices failed to converge:
X_D4_1.D4 X_D4.D4 X_D1.D1 X_D1_1.D1 X_X3.M1 X_X3.M2

I am using TI's PSPICE design for the LM5118 startup model as template. If I modify the value for the ramp resistor (R7), the simulation fails. This is also the case if I modify the value for the soft-start capacitor (C16) or the error amplifier compensation circuit (R4, C17 and C18). 

 

I also tried modifying all values according to the reference design in TIDA-01179, but as expected, the simulation fails as well. 

I found this answer here, suggesting to change the simulation parameters, but this didnt work either. 

See attached PSpice project. 

6431.tida-01179.zip

  • 0
    TI__Genius 17025 points

    Hi Bseck,

    Please expect a reply by tomorrow due to public holiday.

    Best Regards,

    Feng

  • +1 in reply to Feng Ji
    TI__Mastermind 25750 points

    Hi Bseck,

    Thanks for using the e2e forum.
    The suggestion you found in a separate thread should normally reduce risk of convergence issues.
    As you are still seeing problem, I would recommend to simplify the design:
    - Non-ideal FETs or diode can cause convergence issues, so for debugging purposes, I would recommend to try different FET/diode models.
    The are also the parts that PSpice mentions as not converging in the error log

    If you still see errors, I would also recommend to reverse some changes from the TIDA design back to the original testbench, to see when the convergence issues first pops up.

    Best regards,
    Niklas