Other Parts Discussed in Thread: ADS1263
In 4-20mA analog input, the burden resistor is subjected to excessive power/voltage in case of wiring mismatch or the field transmitter failure.
TIDA-00548 employs an input MOSFETs as a current-limiting devices in each channel, which shall be perceived as potentially more robust, accurate and faster mean of protection than any PTC.
The gates of MOSFETs are routed respectively to AIN8 and AIN9 of ADS1263 DAC. These I believe operate in GPIO mode.
What should be the principle of MOSFET gate control in this setup:
What would be over-current detection condition resulting in pulling the GPIO low? Is it an abnormally high conversion result? A one of single or multiple/repetitive occurrences across the stream of samples? What should be a recommended margin between FSR code and over-current trigger code?
What would be your recommendation in a multi channel configuration with sampling rate up to 50SPS/channel:
Shall the respective channel's MOSFET be activated only through the measurement period in the certain channel or permanently? What would be the recommended MOSFET's setup/settling time prior to conversion begins?
Were this issues investigated in this design?