PMP20127: Getting switching ripples on output

DC-DC TI.pdf

Hello Ankit,

The sharp voltage spikes on the output are common on discontinuous topologies, such as this Flyback design.  There are a few things that can be done to try and mitigate these spikes as much as possible.  Please note that all designators that I mention below pertain to the schematic you have provided.

1.  The loop area (i.e. trace inductance) from the secondary winding of the transformer through the rectifying diode (D2), output capacitors, and back to the GND connection of the winding need to be as small as possible.  D4 is not necessary and actually increases the loop area, as well as creates higher power losses, leading to both lower efficiency and higher temperature rise.  I recommend you remove D4 and connect pins 9 and 10 of the transformer directly to the secondary-side GND.

2.  Ceramic capacitors are needed to be placed where C3 and C4 are located.  The C3 position in the circuit is especially critical and requires the placement of a number of high frequency (low ESL) ceramic capacitors, since this is part of the critical path (high di/dt loop).  Large electrolytic capacitors have too high of an ESL to mitigate these high frequency spikes.  It would be a good idea to place a number of ceramic capacitors, such as 10uF, 1uF, 0.1uF, 1nF, and/or 220pF to attenuate the various frequency elements of the output voltage spikes.  You can try placing a number of these and seeing how much each improves the spikes, since each capacitor has varying impedance characteristics at different frequencies.

3.  You might want to try replacing the 1uH L1 inductor with a high frequency ferrite bead.  A properly selected ferrite bead (both current rating and impedance characteristics along with the appropriately selected filtering ceramic capacitors) should reduce the high frequency voltage spikes.  Be aware that ceramic capacitors need to be placed at the C4 position as well to get the best effects of the ferrite bead.

4.  Try connecting C2 to the secondary-side GND instead of the cathode of D2.  At times this is helpful, since it may allow for the smaller loop areas that the snubber can help better attenuate the high frequency spikes.

Not all of the above may be necessary.  There may be one or a combination of a few of the above recommendations that can alleviate the Vout spikes.  It depends on the specific PCB layout and characteristics of the components selected, as well as how low you would like the output ripple and spikes to be.

Regarding the overheating, please remove D4 and connect pins 9 and 10 of the secondary-side winding directly to the isolated GND, as advised above.  Also, D2 seems to be underrated.  I would recommend using at least a 100V-rated diode, as well as a larger package/case size.  At 125V input the spikes across D2 can reach about 90V, as seen in the original PMP20127 design test report.  The diode used in the original design is a D2PAK Schottky that is 8A rated.  This package has noticeably lower junction-to-ambient thermal resistance and will exhibit lower temp. rises.  Also notice the vias that are placed on the cathode copper plane/polygon on the original PMP20127 PCB.