• State TI Thinks Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 52 subscribers
  • Views 150 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

CC2650: cc2650

Sagiv Zeltser
Prodigy 30 points
Part Number: CC2650

Hey,

we designed a circuit using CC2650, we now face an issue that removing the battery and connecting it again will require a reset pulse to be applied to the CC2650, otherwise it is stuck. 

this does not happen all the time.

any idea what can cause that and how to solve it?

p.s

the design is mostly based on the sensortag reference design.

thanks, 

  • 0
    TI__Guru**** 168884 points

    Hi,

    Thanks for your inquiry. In a general sense, these types of intermittent issues with power up/down may be caused by several factors. Specific to your description, they may be due to bouncing supply rails if there is insufficient decoupling or faulty turn on/off circuit, or an unstable or very short assertion of the reset line during power up. You can try to probe your power rails and reset line with a digital oscilloscope and see the transient response during a power up. 

    Specific to the reset line, our reference designs usually have an RC network on the reset pin of the device, which can guarantee the RESET_N pin is asserted long enough to guarantee a stable reset. This is mentioned in table 5.27 of the CC2650 datasheet (a copy of the table in SWRS158B is shown below):

    The RC network is as follows:

    Hope this helps,

    Rafael

  • 0 in reply to desouza
    Prodigy 30 points

    Hey Rafael,

    Out design is the same and still the CC2650 will not turn on after connecting the battery without lowering the nreset after power is on.

    Attached are nreset and vdds signals 

  • 0 in reply to Sagiv Zeltser
    TI__Guru**** 168884 points

    Hi,

    Thanks for sending the additional information.

    The parameter I mentioned in my previous post is the difference between the rising edge of VDDS and RESET_N. Unfortunately, the screenshot does not show this difference in detail (it also has no time/div indication), therefore I can't be sure if the minimum time mentioned in the datasheet is being met.

    Since the design is the same and if you do not see a specific problem with the parts that comprise the reset circuit, as I mentioned before there might be other issues contributing to this behaviour, including software problems.

    In my experience, one software problem that I have seen after a cold boot (from power off) is when variables are not properly initialized before running. What happens is that the first run will fail to run due to bad value (or values) stored in RAM. After a warm reset (i.e., without power off), the RAM value from the first run is initialized properly and the second run succeeds.

    Naturally there might be other contributing factors, thus requiring further investigation.

    Hope this helps,

    Rafael