RF430FRL152H: How to use Clkin for ACLK?

Hi Chris,

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Hi Charles,

Thank you for the information.

According to the -- External Clock Source:  CLKIN/XIN is a source for ACLK (SELA = 2 and OSCOFF = 0)

we check the following settings, but it does not work.

CCSCTL6 = 0x00;

CCSCTL4 = SELA_2 + SELM_0 + SELS_0;

Hi,

 I'm also new to this device. Reading the TRM, XTBYASS should be 1 if you are sourcing XT externally from pin but you are setting the entire CCSCTL6 to -. Can you try setting XTBYASS to 1. Do you see different result?

Hi Charles,

Thank you for the information.

We check and it changes nothing. 

CCSCTL6 = 0x10;

or

CCSCTL6 = 0x00;

Clkin is 32.768KHz

CCSCTL5 = DIVA_2 + DIVM_1 + DIVS_1; 

(DIVA_2 is divide by 4)

And we set the Aclk source from  SELA_2 (CLKIN)  or SELA_1 (LFCLK),  Aclk is always 64KHz

CCSCTL4 = SELA_2 + SELM_0 + SELS_0;

or

CCSCTL4 = SELA_1 + SELM_0 + SELS_0;

Aclk seems source from LF-OSC, even the setting SELA_2 (CLKIN)

Aclk clock source seems not change successfully.

Hi Chris,

  I will suggest you check several things. 

  - Can you measure Clkin to see you are getting a 32kHz input. 

  - What type of Clkin do you have? Is it a external oscillator?

  - Do you see any oscillator fault?

  - Can you show your entire register dump for CCS module?

Hi Charles,

Thank for information.

1. External OSC: TG-3541CE

2. the external OSC is checked to connect to p1.4 and output 32.768KHz

3. We use CCS tool to see the register, but the clkin and TCK is the same pin.

So, I just cannot dump all registers by JTAG when using external OSC.

chris liu said:

3. We use CCS tool to see the register, but the clkin and TCK is the same pin.

So, I just cannot dump all registers by JTAG when using external OSC.

If you can connect to the device, then you can view the registers that record the state of the device that happened before you connect the debugger. I suppose that if there is a clkin fault then by the time you connect with a debugger, the CCSCTL7 register will still have the fault status despite TCK is being used on P1.4. 

Hi Charles,

Thanks for the advice.

(Disconnect the JTAG)

Write CCSCTL6: 0x0010

And the registers are dumped into FRAM and read by NFC:

P1SEL0: 0x0000
P1SEL1: 0x0006
P1DIR:  0x0046
CCSCTL1: 0x0000
CCSCTL4: 0x0200
CCSCTL5: 0x0311
CCSCTL6: 0x0000
CCSCTL7:0x0001
P1OUT:  0x00B0
P1REN:  0x0000

CCSCTL6 is write to 0x0010, but readbacks 0x0000

CCSCTL7 is 0x0001, (XOFFG is 1)

Hi Chris,

  Can you first set CCSCTL7 to zero to clear out the XOFFG flag and also set CCSCTL6 to 0x0010? Let it run and then read back the registers? is the XOFFG bit 1 or 0?

Hi Charles,

 Can you first set CCSCTL7 to zero to clear out the XOFFG flag and also set CCSCTL6 to 0x0010? Let it run and then read back the registers? is the XOFFG bit 1 or 0?

We clear CCSCTL7 =0x0000, then set CCSCTL6 = 0x0010

void DeviceInit(void)
{
	P1SEL1 = 0x00; //P1.6 = 0
	P1SEL0 = 0x00; //P1.6 = 0
	
    P1SEL1 |= 0x06; //P1.1(ACLK), P1.2(MCLK)
    P1DIR |= 0x06;	//P1.1 OUTPUT, P1.2 OUTPUT
    P1REN = 0;

    RFPMMCTL0 = RFPMMCTL0EN_VFREG_BATSWITCH_VDOUB;


    CCSCTL0 = CCSKEY;                        // Unlock CCS

	CCSCTL7 = 0x0000;

    CCSCTL1 = 0;                             // do not half the clock speed
	CCSCTL4 = SELA_2 + SELM_0 + SELS_0;
    CCSCTL5 = DIVA_3 + DIVM_1 + DIVS_1;      // Set the Dividers for ACLK (4), MCLK, and SMCLK to 1
	
    CCSCTL8 = ACLKREQEN + MCLKREQEN + SMCLKREQEN; //disable clocks if they are not being used


    TA0CCTL0 = CCIE;                        // Timer A0 Capture/compare interrupt enable
    TA0CTL = TASSEL__ACLK +                 // Timer_A clock source select -> ACLK
                 MC_1 +                     // Mode control, Timer counts up to the value stored in TA0CCR0
                 ID_3;                      // Input divider -> 1/2 (4MHz/2 = 2MHz) - this is the frequency which goes to comparison register


    TA0CCR0 = 1590; 
	
	CCSCTL6 = 0x0010;

    CCSCTL0_H |= 0xFF;                       // Lock CCS
	
	P1DIR |= 0x04; // P1.2 output

  return;
}

Then, read back the register:

CCSCTL6: 0x0000
CCSCTL7:0x0001

That is a strange thing: we set  CCSCTL6: 0x0010, but readbacks CCSCTL6: 0x0000

And the CCSCTL7: 0x0001

----
Besides, we check and set the TA0CCR0 = 1590, readbacks  TA0CCR0: 0x0636

Those registers should be set correctly by our code.

chris liu said:

1

2

CCSCTL6: 0x0000

CCSCTL7:0x0001

XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

CCSCTL6: 0x0000
CCSCTL7:0x0001

That is a strange thing: we set  CCSCTL6: 0x0010, but readbacks CCSCTL6: 0x0000

And the CCSCTL7: 0x0001

Per my understanding from the datasheet, if CCSCTL7 is first cleared and later you see it become 0x0001 again, it means it is detecting a oscillator failure. Could there be a reset event that causes CCSCTL6 and CCSCTL7 to show the default values?

Thanks for reply.

1. Is it ok that 1.5V OSC for P1.4?

2. Is there any sample code for external clock?    We would check our firmware or hardware.

Hi Chris,

  I need to consult with the expert was supporting this device in the past as I'm also new to this device. From what I can see, your code seems to be fine but I don't know for sure. What is the CCSKEY? I want to make sure you write to bits 15:8. 

Hi Charles,

Thanks for relay.

CCSKEY would be defined in the rf430frl152.h

#define CCSKEY                 (0xA500)       /* CCS Password */

Hi Chris,   

The CSSKEY looks correct to me. I will need to consult with the expert what is wrong with the Clkin setup.

Hi Chris,

  Checking with our expert, he has the below suggestions.

• Table 6-12 in the datasheet (page 37) says JTAG mode needs to be disabled for CLKIN function.
• The RF430FRL152H is based on the MPS430L092, maybe its example code from MSP430-ware can help to get it working (The pins seems to be mapped differently at the L092, but the methodology might be same.) https://dev.ti.com/tirex/explore/node?node=A__AOSvvG7PkZslF17uiWtOMA__msp430ware__IOGqZri__LATEST

Hi Charles,

Thanks for reply.

1. According the data sheet, setting p1sel0.6 and p1sel1.6 to disable JTAG.

Our code is already set as follows:

	P1SEL1 = 0x00; //P1.6 = 0
	P1SEL0 = 0x00; //P1.6 = 0

2. There is no different between our code and MSP430- sample code. 

CCSCTL4 = SELA_2;

Hi Chris,

  I really don't know the cause to the problem. Can you try a few things?

 - Provide the schematic of the design.

- Show the scope cap waveform for Clkin. Is it in the voltage range for RF430?

- Your TG-3541CE has an OE input? How are you controlling this input?

- Do you have the same problem on all the custom boards you have?

- Can you repeat the problem on a EVM board?

Hi Charles,

According to our EE: 

1. The schematic  is as Link

https://www.dropbox.com/scl/fi/px0w7b16ziu9ru7iyeu22/SCHEMATIC_For-OSC.pdf?rlkey=de6snssz2smnyg3ktfgy2htx0&st=80w0h0a0&dl=0

2. As picture, 1.5V, 32.768KHz

3. OE connect to VCC directly. When VDDSW is power on when NFC switch on, OE get high.

Hi Chris,

  Can you attach the schematic here directly. My company blocks from accessing 3rd party cloud storage. 

  Looking at the waveform, it looks normal to me but I really don't know what is wrong. 

  Can you answer the other two questions I have?

      - Do you have the same problem on all the custom boards you have?

      - Can you repeat the problem on a EVM board?

Hi Charles

I'm EE and share schematic of parts surrounding RF430FRL152H.

The signal as shown is (clock, 32.768KHz, 1.5V) connected to Pin22 (P1.4, CLKIN).

The power of OSC is connected to VDDSW. (We've tried connected to VDDB, but the result is the same.)

Hi Nick,

  I don't see a problem with your schematic. 

chris liu said:

CCSCTL4 = SELA_2 + SELM_0 + SELS_0;
CCSCTL5 = DIVA_2 + DIVM_1 + DIVS_1; // Set the Dividers for ACLK (4), MCLK, and SMCLK to 1

As far as I can tell, in your CCSCTL4 register, you only choose CLKIN for ACLK. However, you choose HFCLK for SMCLK and MCLK.  Can you set SMCLK and MCLK to use CLKIN as well? E.g. CCSCTL4 = SELA_2 + SELM_2 + SELS_2;

Please also make sure all the flags are set to zero accordingly. See below highlighted in yellow. 

Dear Charles,

Thanks for replay.

We checked the code that is the same as MSP430 sample code:

CCSCTL4 = SELA_2 + SELM_2 + SELS_2;

CCSCTL5 = DIVA_0 + DIVM_0 + DIVS_0; 

while(1);

It still seems not source from clkin.

oscoff is controled by the low power mode. 

.

Our test condition is active mode, but LPM0~4.

Chris,

  I wanted to make sure there is nothing wrong with the device. Can you do some experiments as I kind of run out of ideas.

- If you do not use P1.4 for Clkin but rather use it as TCK, can you connect to the device through JTAG?

- If you do not use P1.4 for Clkin but rather use it in GPIO mode, can you detect and generate interrupt for a rise edge or fall edge while the external oscillator is still connected to P1.4?

- Can you swap in another RF430 device to your board? Can you repeat the same issue? I want to know if the issue is only to one device or all devices. I want to make sure if the problem is not because of a damaged pin. If all devices have the same issue then it must be some configuration issue. 

Dear Charles,

Thanks for replay.

According to the P1.4 multi-function table, by only disabling JTAG mode that changes to the CLKIN function.
But, disabling the JTAG mode, it can be function: P1.4/timer/SMCLK/CLKIN.

CLKIN function that dont care P1DIR.x/P1SEL1.x/P1SEL0.x, 

How does chip know which function that user want to use?

If the paths of CLKIN and P1.4 are different, CLKIN should be always enabled and easy to use after JTAG is disabled. 

2. We check the other board, and it still can not source from CLKIN.

3. JTAG can not be used after P1.6 is disabled.

Hi Charles,

Did you get the reply from TI Dallas that this CLKIN (external OSC) is built in RF430FRL152H or not?

And how it works from schematic in IC?

Thanks.

chris liu said:

If the paths of CLKIN and P1.4 are different, CLKIN should be always enabled and easy to use after JTAG is disabled. 

My purpose to test JTAG mode and GPIO mode is to determine if the physical pin is bad or not. If the physical pin is damaged, then both JTAG and GPIO mode will also fail. This is the reason for testing. But if you say all the boards have the same Clkin issue then it is not a hardware issue. 

Per the block diagram, the CLKIN is directly routed to the CCS and the input pad is shared with all receiving modules (e.g. CCS, JTAG, GPIO).

NickSY Huang said:

Did you get the reply from TI Dallas that this CLKIN (external OSC) is built in RF430FRL152H or not?

There is no reason to believe that the feature is not supported when it is documented in the datasheet and TRM for years. 

I'm looking for expert to help this post now. 

I will be out of office with limited access to internet until next Tuesday.