Other Parts Discussed in Thread: CC3220S
Hi,
I want to increase the drivestrength for SPI Clock on Pin 5. I see that you can do this by setting bit 7:5 of the GPIO_PAD_CONFIG_x register (page 587 of the Technical Reference Manual (TRM)).
What I've done so far are:
1. Added the following in Board.h
#define Board_GPIO_P05 CC3220S_LAUNCHXL_GPIO_14 |
3. Added the following in the enum, CC3220S_LAUNCHXL_GPIOName of CC3220S_LAUNCHXL.h
CC3220S_LAUNCHXL_GPIO_14, |
4. Added the following in gpioPinConfigs[] of CC3220S_LAUNCHXL.c
GPIOCC32XX_GPIO_14 | GPIO_CFG_OUT_STR_HIGH, |
But there were no changes to the output. I have a feeling that this isn't the correct way to do it. Any help would be much appreciated :)
