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PGA 280 Queries

Abhay Kothari1
Prodigy 240 points
Other Parts Discussed in Thread: PGA280

Hi ,

We are using the PGA 280 in our project , Please address the following queries

>>If we use GPIO4 as an input BUFTin , does the setting of BUF Timeout Register / Register 3 have any effect

>>Do we need to use the buffer trigger 'T'in the upper nibble of the byte of the SPI addressing scheme , if GPIO 4 is used as BUFTin ??

>>Whats is the difference between the bits of register 4 and register 10 , they seem to have the same error flag bits ,Please elucidate

>>How do we use Register 6 & 7 ?

>>Does the BUFPol bit on the Register 10 change the BUFA pin polarity to active high or low ?

>>What is the function of LTD bit /bit 7 on register 11

Regards
Abhay

  • 0
    TI__Mastermind 27715 points

    Hello Abhay,

    If GPIO4 is used as the input BUFTin, the setting of the BUF timeout has no effect. The buffer is activated after 3 to 4 clock cycles.

    You do not need to use the buffer trigger in the SPI write if you use GPIO4 as BUFTin.

    Register 10 can be used to configure error flag settings, while register 4 is where the error flags can be read. There is some overlap between registers 4, 10, and 12 - please read the bit descriptions carefully.

    You use register 6 and 7 to open or close the various switches of the input network. '0' is an open switch, '1' is a closed switch. Figure 44 in the PGA280 data sheet shows the input switch network with all labels.

    The BUFA Pol bit can be used to set the BUFA pin active polarity to either high or low. Set to '0' for active high, set to '1' for active low.

    The LTD bit in register 7 is used to automatically clear error flags, if you prefer to monitor them in real time. Once an error condition is met, the error flag will set and then be automatically cleared after the number of clock cycles specified by FLAGTIM[0:3]. If LTD is set to '0,' error flags will remain set until cleared by a register write to their specific bits.

    Best regards,

    Ian Williams
    Linear Applications Engineer
    Precision Analog - Op Amps

  • 0 in reply to Ian Williams
    Prodigy 240 points

    Hi Ian,

    Thanks for the reply ,

    Are the error flags in Reg 10 activated by setting them low or high ?? I have observed that they are low by default/after POR

    With regards to the LTD bit 

    U mean register 11 right  

    The data sheet mentions the following : 

    "Individual error signals are not latched if this bit is set to '1'"  ,

    Does this mean that if i set this bit to one during configuration , i will be able to see EF flag only when multiple errors arise ??

    Regards

    Abhay

  • 0 in reply to Abhay Kothari1
    TI__Mastermind 27715 points

    Hi Abhay,

    You are correct - the POR values in Register 10 are all '0' by default. The error flags are ACTIVE when their bits are low. Writing a '1' to one of these bits will disable that error flag.

    Yes, I meant the LTD bit in Register 11. If you set the LTD bit to '1', the EF flag will be automatically cleared after the number of clock cycles set by FLGTIME[0:3]. Therefore, you would need to continuously monitor the flag for errors as you would only have a small window to observe them before they are cleared. If you leave the LTD bit at its POR value of '0,' error flag conditions will latch - that is, they will remain high until manually cleared.

    Best regards,

    Ian Williams