PGA112: PGA112 - V out not at Vref, at Vdd

Roger Dallas

Part Number: PGA112

Hello:

Really hoping I can get some help on this issue. Using a PGA112, connected as shown in the attached image, "PGA112_Connect.jpg"

Vdd is at 3.3V, Vref is at midpoint of 1.65, and connected to PGA112's vref input. If I am using CHN1, I would then expect the DC at the output to be at Vref. For whatever reason, and no matter what I write to the PGA112, the output wants to stay at Vdd. Please refer to the other attached images, PGA112_CS_CLK and PGA112_CS_DATA. I have divided down the SPI interface prescaler by 64 to allow eons of time for setup and hold delays, etc. Everything appears to be good. I am writing 0x2A12, which (from pg.27 of data sheet) is WRITE and CHN1 selection bit.

Can anyone see a problem...thanks for your help!

over 7 years ago

0 Roger Dallas over 7 years ago

Prodigy 160 points

Hi,
Problem solved! IT turns out there was a minute solder bridge across 2 pins. Sorry to bother and thanks for being available to help.

Gary

0 Errol Leon6 over 7 years ago in reply to Roger Dallas

TI__Expert 5830 points

Hello Roger,

I am glad you were able to figure it out. It is not bother at all. Let us know if you have anymore questions.

Best,

Errol Leon
Texas Instruments
Precision Op Amps

0 Roger Dallas over 7 years ago in reply to Errol Leon6

Prodigy 160 points

This is actually a very good part. Even under high gains, it deviates little at Vref, and signal remains clean.

Thanks again,
Gary

0 Fernando Prokopiuk over 7 years ago in reply to Roger Dallas

Prodigy 80 points

Can you share your code? Thanks in advance.

0 Roger Dallas over 7 years ago in reply to Fernando Prokopiuk

Prodigy 160 points

// SETUP for STM32F4 processor (uses CMSIS)

// DEFINES USED

#define PGA112_CS       GPIO_Pin_7
#define PGA112_SCK      GPIO_Pin_13
#define PGA112_MISO     GPIO_Pin_14
#define PGA112_MOSI     GPIO_Pin_15

#define SET_GAIN_1      (uint16_t)0x2A11
#define SET_GAIN_2      (uint16_t)0x2A11
#define SET_GAIN_4      (uint16_t)0x2A21
#define SET_GAIN_8      (uint16_t)0x2A31
#define SET_GAIN_16     (uint16_t)0x2A41
#define SET_GAIN_32     (uint16_t)0x2A51
#define SET_GAIN_64     (uint16_t)0x2A61
#define SET_GAIN_128    (uint16_t)0x2A71

void initialize_SPI2(void)
{
    SPI_InitTypeDef SPI_InitStruct;
    GPIO_InitTypeDef GPIO_InitStructure;

    // enable peripheral clock - SPI Clock
    RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE);

    // enable GPIO E for PE7 (SPI gain select)
    RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOE, ENABLE);
    RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB, ENABLE);

    /* Configure the chip select pin to PE7 */
    GPIO_InitStructure.GPIO_Pin = PGA112_CS;
    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
    GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_25MHz;
    GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
    GPIO_Init(GPIOE, &GPIO_InitStructure);
    //initially set (PE7) CS high
    GPIOE->BSRRL |= PGA112_CS;

    GPIO_InitStructure.GPIO_Pin = PGA112_MOSI | PGA112_MISO | PGA112_SCK;
    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
    GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_25MHz;
    GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
    GPIO_Init(GPIOB, &GPIO_InitStructure);

    // use ALTERNATE MAPPING function
    GPIO_PinAFConfig(GPIOB, GPIO_PinSource13, GPIO_AF_SPI2); //connect pin 13 port B to the SPI2
    GPIO_PinAFConfig(GPIOB, GPIO_PinSource14, GPIO_AF_SPI2); //connect pin 14 port B to the SPI2
    GPIO_PinAFConfig(GPIOB, GPIO_PinSource15, GPIO_AF_SPI2); //connect pin 15 port B to the SPI2

   // need only half-duplex
    SPI_InitStruct.SPI_Direction = SPI_Direction_1Line_Tx; // set to TX only

    SPI_InitStruct.SPI_Mode = SPI_Mode_Master;     // transmit in master mode, NSS pin has to be always high
    SPI_InitStruct.SPI_DataSize = SPI_DataSize_16b; // one packet of data is 16 bits wide
    SPI_InitStruct.SPI_CPOL = SPI_CPOL_Low;        // clock is low when idle
    SPI_InitStruct.SPI_CPHA = SPI_CPHA_1Edge;      // data sampled at first edge
    SPI_InitStruct.SPI_NSS = SPI_NSS_Soft | SPI_NSSInternalSoft_Set; // set the NSS management to internal and pull internal NSS high

    // don't overclock the PGA112, no need to anyhow
    SPI_InitStruct.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_64; // SPI frequency is APB2 frequency / 4
    SPI_InitStruct.SPI_FirstBit = SPI_FirstBit_MSB;// data is transmitted MSB first
    SPI_Init(SPI2, &SPI_InitStruct);

    SPI_Cmd(SPI2, ENABLE); // enable SPI2
}

void SPI2_send(uint16_t data)
{
    // send gain setting to PGA112
    GPIOE->BSRRH |= PGA112_CS; // set PE7 (CS) low
    SPI2->DR = data; // write data to be transmitted to the SPI data register
    while( !(SPI2->SR & SPI_I2S_FLAG_TXE) ); // wait until transmit complete
    while( SPI2->SR & SPI_I2S_FLAG_BSY ); // wait until SPI is not busy anymore
    GPIOE->BSRRL |= PGA112_CS; // set PE7 (CS) high
}

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PGA112: PGA112 - V out not at Vref, at Vdd