Linux/AM5728: LJCB_CLK input AC specifications

Will,

The following additional information needs to be added to the AM572x DM:

As it states here, you need to properly configure the clock generator to provide a high-quality HCSL-complaint clock.

Tom

Previous post edited to correct the figure.

WTMEC_Will,

Section 2.1.3 of the PCIe CEM spec provides the REFCLK AC Specifications.  Section 4.3.7 of the PCIe Base spec also provides Refclk AC Specifications including 5GT/s.  These are the relevant AC specifications for the LJCB clock input to the PCIe module.

Tom

WTMEC_Will,

A colleague provided a more clear direction for these specs.  You should refer to:

• Section 2.1.3 of the CEM spec for REFCLK DC and timing requirements

• Section 4.3.7 of the Base Spec for REFCLK jitter requirements

Tom

Vijay,

My previous post was sufficient.  The tables in the referenced sections are applicable.

Tom

Vijay,

The HCSL or LVDS compliance testing can only be done on the driver side of the capacitors.  Once the clock signal goes through the capacitors, the DC level is removed.  Therefore, to validate the signal matches the compliance table, the measurements must be made on the driver side of the capacitors.

Tom

Denny,

Responses below:

Q: As AM57xx TRM mentioned "RX is a clock slicer that receives HCSL or LVDS differential clock".

A: This statement does not mean that DC coupling can be used for either HCSL or LVDS.  It means that with proper circuitry, both HCSL and LVDS clock sources can be used.

Q: 1.  So why the EVM add 0.1uf capacitor here? When adding the capacitor, the DC will be removed, then it can't meet PCIe 2.1.3 spec at AM57xx ljcb_clkp/n pin.

A: As stated in the Data Manual excerpt, the series capacitors are only required if an LVDS clock source is used.  This eliminates the DC bias voltage that would violate the single-ended voltage limits on the ljcb pins.  If an HCSL-compliant clock is used, it can be DC-coupled to the ljcb pins.  However, there is no negative effect to adding DC-blocking caps with an HCSL clock.

A: HCSL compliance or LVDS compliance is not required at the ljcb pins.  HCSL compliance or LVDS compliance is required at the clock that is provided for the ljcb pins.

Q: 2.  Does the DC(Vcross) is not necessary at AM57XX side?

A: The DC(Vcross) spec is part of the requirements for HCSL compliance per the PCIe spec chapters.  This must be met when qualifying the HCSL clock source.  If series capacitors are implemented when using an HCSL clock source, the HCSL compliance cannot be verified at the ljcb pins.  HCSL compliance must be verified at the input to the series capacitors.

A: The DC(Vcross) spec is not required at the ljcb input pins.  The signal at these pins can be balanced at VSS.

Tom

Vijay,

No.  The ljcb pins cannot withstand the DC levels on a differential pair that contains an LVDS-compliant signal.  The series capacitors are needed to block this DC bias.  However, if you want to probe to validate that an LVDS-compliant signal is attached, you must probe on the driver side of these capacitors where the DC bias is still present.

Tom

Vijay,

From re-reading your previous post, I believe you do not fully understand the precise meaning of your words.  When you say a signal is compliant to LVDS, then this includes all parts of the spec including AC swing min and max as well as DC bias.  That is why I keep saying the pins cannot accept a signal compliant to LVDS.  The signals can accept the AC swing levels for LVDS but they cannot accept the DC bias.  That is why the series capacitors are required.

Tom

Vijay,

I cannot be more clear than I was in my last 2 posts.

Tom