LMK00101: Is there a TI Clock buffer which its input clk is 3.3v tolerable while its VDD powered by 2.5V ?

Ohad Fundoianu

Intellectual 540 points

Part Number: LMK00101
Other Parts Discussed in Thread: CDCLVC1112, CDCLVD1208, SN74LV4T125, SN74AUC244

In any Clock buffer I found in here, the Vih in the Recommended operatings is defined to be VDD+0.3v/0.5v.

Is there a clock buffer in which the Vih can tolerate 3.3v evemthough the VDD=2.5v ?

over 5 years ago

0 Lane Boyd over 5 years ago

TI__Genius 16845 points

I quickly looked through the portfolio, but unfortunately I didn't find a device that would meet this requirement.
3.3V input amplitude is the amplitude of a LVCMOS clock. You might consider CDCLVC1112 if you can supply VDD=3.3V.

Kind regards,
Lane

0 Ohad Fundoianu over 5 years ago in reply to Lane Boyd

Intellectual 540 points

Lane Boyd said:

I quickly looked through the portfolio, but unfortunately I didn't find a device that would meet this requirement.
3.3V input amplitude is the amplitude of a LVCMOS clock. You might consider CDCLVC1112 if you can supply VDD=3.3V.

Kind regards,
Lane

Hi,

OK, LVCMOS is good, that's what I need, I did not find in any of the CDCxxxx series nor the LMKxxxxx series such a clock buffer which is 3.3v tolerant while it is powered by 2.5v.

Thanks,

Ohad

0 Shawn Han over 5 years ago in reply to Ohad Fundoianu

TI__Genius 9920 points

Hi Ohad,

Refer to 2.5V differential output clocks
www.ti.com/.../products.html

For example, CDCLVD1208
www.ti.com/.../cdclvd1208.pdf

3.3V LVCMOS input could be divided by resistors in 2.5V for CDCLVD1208

Best Regards,
Shawn

0 Ohad Fundoianu over 5 years ago in reply to Shawn Han

Intellectual 540 points

I cannot do that since I'm talking about at least 10 signals needed to be shifted from 3.3v to 2.5v. Better thing to do is to use a 3.3v_to_2.5v level shifter. Do you have any recommendations for such a device ?

0 Shawn Han over 5 years ago in reply to Ohad Fundoianu

TI__Genius 9920 points

If there are 10 different 3.3V LVCMOS signals need be shifted to 2.5V LVMCOS signal, level shift is a good choice.
For example, SN74LV4T125. TI level shift expert would continue to support you.

0 Emrys Maier over 5 years ago in reply to Shawn Han

TI__Guru* 96591 points

Hi Ohad,
I would recommend using an octal buffer like the SN74AUC244. The inputs can be up to 3.6V with the supply set to 2.5V.

Clock & timing

Clock & timing forum

LMK00101: Is there a TI Clock buffer which its input clk is 3.3v tolerable while its VDD powered by 2.5V ?