Other Parts Discussed in Thread: LMK04616, LMK04610, LMK04828, AFE7686, CDCM6208
Hello,
We are using LMK04821 in one of the enodeB design.
Currently the reference input of 122.88MHz is applied to CLKIN0.
We have provided option for external clock of 10MHz/ 30.72MHz for CLKIN1 input.
The JESD204B clocks used are 245.76MHz on DCLK, and 120KHZ on SDCLK with input clock of 122.88MHz.
Pls could you let me know whether it is possible to generate JESD204B clocks used are 245.76MHz on DCLK, and 120KHZ on SDCLK with input clock of 10MHz or 30.72MHZ external clock.
Regards,
Sumathi