This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LMK04828: LMK Loop Filter Components

Part Number: LMK04828

Hello,

We are about to do a second spin of our clocking board. We will be using the LMK04828, with a 100MHz LVCMOS clock going into OSCin single ended. (P/N: Connor Winfield VX545). Going into the CLKin1 port is a 10MHz atomic clock.

Here are the loop filter compnents we are going to use. 

PLL1:

R1: 0.082 KOhm

C2: 22000nF

C1: 1500nF

PLL2:

R1: 0.820KOHms

C2: 2.2nF

C1: 0.047nF

I have also Attached PLLatinum sims for each PLL. 

And also the hex values that we are using. 

I wanted to make sure that this was going to work. Our first go around of this has not been successful. Any help will be greatly appreciated. 

Thank you. 

6560.HexRegisterValuesLMKtmp.txt
R0 (INIT)	0x000090
R0	0x000000
R2	0x000200
R3	0x000306
R4	0x0004D0
R5	0x00055B
R6	0x000600
R12	0x000C51
R13	0x000D04
R256	0x010003
R257	0x010155
R258	0x010255
R259	0x010301
R260	0x010402
R261	0x010500
R262	0x0106F9
R263	0x010755
R264	0x010818
R265	0x010955
R266	0x010A55
R267	0x010B01
R268	0x010C02
R269	0x010D00
R270	0x010EF1
R271	0x010F06
R272	0x011018
R273	0x011155
R274	0x011255
R275	0x011301
R276	0x011402
R277	0x011500
R278	0x0116F1
R279	0x011706
R280	0x011878
R281	0x011955
R282	0x011A55
R283	0x011B01
R284	0x011C02
R285	0x011D00
R286	0x011EF1
R287	0x011F06
R288	0x012008
R289	0x012155
R290	0x012255
R291	0x012300
R292	0x012402
R293	0x012500
R294	0x0126F9
R295	0x012700
R296	0x012808
R297	0x012955
R298	0x012A55
R299	0x012B00
R300	0x012C02
R301	0x012D00
R302	0x012EF9
R303	0x012F00
R304	0x013006
R305	0x013155
R306	0x013255
R307	0x013300
R308	0x013402
R309	0x013500
R310	0x0136F9
R311	0x013700
R312	0x013800
R313	0x013900
R314	0x013A0C
R315	0x013B00
R316	0x013C00
R317	0x013D08
R318	0x013E03
R319	0x013F00
R320	0x01400F
R321	0x014100
R322	0x014200
R323	0x014311
R324	0x01440E
R325	0x01457F
R326	0x014610
R327	0x01471B
R328	0x014802
R329	0x014902
R330	0x014A02
R331	0x014B06
R332	0x014C00
R333	0x014D00
R334	0x014EC0
R335	0x014F7F
R336	0x015001
R337	0x015102
R338	0x015200
R339	0x015300
R340	0x015478
R341	0x015500
R342	0x015601
R343	0x015700
R344	0x015896
R345	0x015900
R346	0x015A0A
R347	0x015BDF
R348	0x015C20
R349	0x015D00
R350	0x015E00
R351	0x015F0B
R352	0x016000
R353	0x016101
R354	0x016224
R355	0x016300
R356	0x016400
R357	0x016501
R369	0x0171AA
R370	0x017202
R380	0x017C15
R381	0x017D33
R358	0x016600
R359	0x016700
R360	0x01680C
R361	0x016959
R362	0x016A20
R363	0x016B00
R364	0x016C00
R365	0x016D00
R366	0x016E13
R371	0x017300
R8189	0x1FFD00
R8190	0x1FFE00
R8191	0x1FFF53
PLL_OSCin_100MHz_20190813.zip

  • Hi Scott,

    Checking the hex values and the loop filter simulations, it looks like everything should work. That being said, it looks like the loop filter values were the same for PLL2 as they were in the previous revision of the board in https://e2e.ti.com/support/clock-and-timing/f/48/t/825576, and you indicated that it was PLL2 which was causing locking problems. For testing purposes (if possible), it might be a good idea in the next spin to split the routing for the OSCin port with an optional 0Ω resistor to an SMA connector, so that you can directly feed OSCin with a source provided by a signal generator for debugging. That way you can isolate PLL2 from PLL1 and work on each PLL separately if debugging is required.

    Regards,

  • Thank you for the response. We now have lock on the older spin of our board. These values will be for the new spin. We really appreciate you looking into the values for us. We will look into adding in a 0 ohm resistor to inject a sig gen into the LMK. Thank you for your time. 

    -Scott Okuma