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LMX2594EVM: State Machine Clock effects

user5941540
Intellectual 280 points
Part Number: LMX2594EVM

Hi !

We have done a set of tests of the evalboard, especially to see the spurious levels. We noted the presence of spurs around the main signal which are located at Fout%Fosc. Using the register R1 to control the Cal_clk_div parameter, we have seen that if we divided the state machine clock by 2 or 4, the level of those signals can be reduced.

As we are using the Full Assist mode only, we would like to know if there is a way to disable the state machine clock, as we do not use the VCO calibration ? Or maybe you know a way to further reduce the Fout%Fosc spurs ?

Thanks by advance

Stephane

  • 0
    TI__Guru* 81740 points

    Hi Stephane,

    You can set R2[10]=0 to disable state machine clock.

  • 0 in reply to Noel Fung
    Intellectual 280 points

    Hi Noel,

    Thanks for the answer, the level of some spurs is indeed better, but not all of them ! I will keep doing my tests.

    It seems this PLL has some hidden registers ! Do you have a complete map that you can share with us ? (I fully understand if that's not possible)

    Stephane

  • 0 in reply to user5941540
    TI__Guru* 81740 points

    Hi Stephane,

    We cannot share all of them, but we can share those that are really useful for you. 

  • 0 in reply to Noel Fung
    Intellectual 280 points

    Hi !

    I've done some tests disabling the state machine clock. That's really good, spurious due to the machine clock aren't insignificant (more than 10 dB for some of them). I think I'll keep the state machine clock disable for now but I want to be sure that configuration will not be an error so:

    -- Do you know if there are adverse effects in that case ? I use the PLL in Full Assist mode to obtain the best lock time possible, and I'm afraid to have in the next few weeks bad news that will force me to let the state machine clock run. So if you are aware of some failures using that configuration, that would be great to know that.

    Change of topic, for me, 3 parameters are important when we're talking about a PLL:

    -- Phase Noise

    -- Spurious

    -- Lock Time

    Tell me if I'm wrong, but it seems the aim of calibration algorithm is to optimize the phase noise (right ?). But that point can be done at the expense of the two others parameters. During my tests, I've seen that 75% of my lock time measurements are less than 30 µs. BUT, some of them can last more than 150 µs. Those tests were done in Full Assist mode, using calibration data from the No Assist mode (VCO_SEL, CAPCTRL and DACISET). I've also seen that using the calibration data, some frequency configurations gave me a spectrum full of bad spurs, BUT, changing values of VCO_SEL, CAPCTRL and DACISET gave me a better spectrum AND a better lock time. My question is:

    -- Do you have a specific way to obtain:

    -- A good lock time ?

    -- A good spectrum ?

    -- Both of them ?

    Thank you by advance

    Stephane

  • 0 in reply to user5941540
    TI__Guru* 81740 points

    Hi Stephane,

    Do you have TI representative supporting you? Let's bridge together over email.