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Output Synchronization in Clock Synthesizer CDCE6200

vijetha hn
Expert 1230 points

Hello there,

I am using Clock synthesizer CDCE6200 for generation of 5 nos of LVDS clock (250MHz); configured by a Max V CPLD IC through SPI interface.

Related to Output synchronization (SYNCn pin and SYNCn bit) of CDCE6200, I have couple of queries:

1. Currently I am giving continuous LOW signal on SYNCn pin (pin number 14) from CPLD and setting SYNC bit (R8.8) as 1. Whether this is proper way of synchronization? My question is whether SYNCn pin (Pin 14) should be always LOW or it should be a LOW to HIGH pulse? If it is LOW to HIGH transition, how long the pin should be LOW?

2. I am using secondary referance (50 MHz, crystal oscilator) and VCO1. Through the synthesizer Tool I have all the values to be set.

My query is what will be the time taken by VCO1 to lock and output the frequency vale (in our case 1000MHz) after Configuration? 

Hope my question is clear to you. Please answer these queries to verify my design.

Regards,

Vijetha

  • 0
    TI__Genius 10320 points

    Hi Vijetha,

    Please note that the SYNC pin is active Low, so by driving this pin low, all outputs will be in High Z until SYNC is released. There is an internal 150 kOhm pull up. If you wish to Sync via SPI (bit R8.8), then SYNCn can be left floating or set to logic '1'. If the SYNCn pin is to be used, the minimum low time is 100 ns, while still meeting rise/fall time specs.

    Please see the DS section named Start-up Time Estimation (pg 67) for approximation of lock time.

    Gabe