Phase offset of CDCVF855

g.f.

Other Parts Discussed in Thread: CDCVF855

Hi,

I have questions about CDCVF855.

Q1.
In CDCVF855 datasheet page.6, there are value of "static phase offset" as +/-50ps.
Is this "phase offset" means that variation in CLK and FBIN is within +/-50ps?

Q2.
"Dynamic Phase Offset" isn't specified in in the CDCVF855 datasheet.
Is this means that this variation don't need to be considered?
So, should user prescribe by the timing of "static phase offset"?

best regards,
g.f.

over 9 years ago

0 Arvind Sridhar over 9 years ago

TI__Mastermind 24205 points

Hi g,f,

1) Figure 5 on Page 8 of the datasheet has the definition for the static phase offset. It is defined as the average offset between CLK and FBIN

2) Our part is compliant to JESD82 standard which includes only static phase offset definition

Regards

Arvind Sridhar

0 g.f. over 9 years ago in reply to Arvind Sridhar

Guru 15510 points

Hi Arvind,

Thank you for the reply.

So,do you mean that user don't need to care about the dynamic phase offset,
is it correct?

best regards,
g.f.

0 Arvind Sridhar over 9 years ago in reply to g.f.

TI__Mastermind 24205 points

Hi g.f.

My understanding from talking to the applications engineer responsible for supporting this device is that the JESD82 standard does not explicitly call out for the dynamic phase offset specification.

Regards

Arvind Sridhar

Clock & timing

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Phase offset of CDCVF855