LMK03328: How long does it take for VCO Calibration ?

Kawai-san,

A1) 4 ms (typ) is the overall PLL startup time, which includes VCO wait time (0.4 ms interval), PLL wait time (0.3 ms intervals) for VCO calibration,  and final PLL closed-loop settling (based on PLL bandwidth).  VCO wait time interval is selected by PLLx_VCOWAIT bits and is a delay before VCO calibration.  The PLL wait time is selected by PLLx_CLSDWAIT bits; this is the dominant time interval since it can repeat several cycles while searching for the optimal VCO cap code during calibration before releasing for final PLL closed-loop settling.  

A2) Longer VCO wait may not be necessary for calibration, but can be made longer to allow more delay time before VCO calibration begins, such as if the PLL input clock is not yet stable.  Typically, a PLLx_CLSDWAIT setting of 0.3 ms is fine for both integer and fractional mode with normal/wide loop bandwidth of > 100 kHz.  Longer PLLx_CLSDWAIT (30 ms or 300 ms) is only needed for narrow loop bandwidth, like <1 kHz.

A3) I don't expect anything to happen, but avoid it if possible.

A4) The VCO wait time can be reproduced by external script, such as by adding delay time before releasing the chip or PLL reset via software bit.  However, an external script cannot replace the PLL wait time, which is an internal timer for the internal PLL controller to wait in each VCO cap code cycle during calibration.

For example, below is a scope capture showing the loop filter voltage (LFx pin) during PLL startup/calibration.  The cursors indicate the VCO wait interval (0.4 ms) initiated by a soft reset event.  After the VCO wait interval, you see the loop filter voltage has discrete steps while the PLL controller searches for the optimal VCO cap code (~6 cycles) before calibration ends.  The PLL closed-loop settling interval is negligible in this example since the loop bandwidth is wide and settling time is much faster compared to the other wait times.

Regards,
Alan

A5) Yes, VCO cal should happen after reference clock is present and stable in frequency/amplitude.

A6) Auto-SYNC occurs after VCO calibration and PLL lock detected on device power-on/reset initiated by PDN pin (hard reset) or soft reset bit.  The output divider settings are loaded into registers on power-up from EEPROM, so these dividers should already be configured before Auto-SYNC occurs.  If the output divider is changed by I2C interface after Auto-SYNC occurs, a manual SYNC can be issued to phase-align the outputs.

Regards,
Alan