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CDCM6208: LVDS - DC vs AC specifications

Elder Costa17
Expert 2825 points
Part Number: CDCM6208

I find the data sheet specifications Vcm-ac and Vcm-dc confusing.

Assuming 1.80V VDD_Yx_Yy, Vcm-dc is 1.67V (1.80V - 0.13V) and output positive peak would be above VDD_Yx_Yy. This conclusion may be caused by my misunderstanding of the specification. Could you please clarify?

OTOH the Vcm-ac spec is VDD_Yx_Yy-0.76V which would mean 1.04V (VDD_Yx_Yy = 1.80V). Any chance ac and dc specs are swapped in the data sheet? 1.04V Vcm would allow outputs to drive LVDS inputs without AC coupling.

Thank you very much in advance.

  • 0
    TI__Expert 5325 points
    Hello Elder Costa17,
    our expert for this device will clarify your questions.

    Best regards,
    Patrick
  • 0 in reply to Patrick Kammermayer
    Expert 2825 points

    Hello, Patrick,

    I look forward to it as I depend on it to close the design.

    Once I  get there I will post the schematics for review, if that`s OK.

    Thanks.

    Elder.

  • 0 in reply to Patrick Kammermayer
    Expert 2825 points

    Hi, any hints on this question?

    I am attaching the schematics for review. I am assuming it is possible to connect directly without AC coupling but I do need your input on this.

    The capacitors and terminators with DC bias would add complexity and I would like to avoid it if possible.

    For whats worth, five outputs will be connected do CDCUN1208 clock buffers, two to an FPGA (built in terminators) and one to a D/A.

  • 0 in reply to Elder Costa17
    Expert 2825 points

    Adendum. The bottom line is if CDCM6802 supports the following connection and, if affirmative, what would be the Vcm.

  • 0 in reply to Elder Costa17
    Expert 2825 points

    Hello,

    Is the lack of an anwser a hint of what I want to do is not possible?

  • 0 in reply to Elder Costa17
    TI__Expert 8865 points
    Hello Elder
    The difference is in the test condition. VCM-DC is measured with 50 ohm on chip termination, while VCM-AC is measured by using ac coupling and receiver termination. Please refer to the test conditions in the spec tables.
    I would recommend to use IBIS mode to simulate your load condition.
    Best regards
    Puneet
  • 0 in reply to Puneet Sareen
    Expert 2825 points

    Hi, Puneet.

    Yes, I understand the specs are related to test conditions. The problem is that it does not help much when it comes to how to deploying the chip. At least it did not help me. Data sheet and dev board documentation do not provide much information on specific implementation. I am using it to have clean clocks to a fairly low frequency acquisition system; maybe for telecom folks the chip seems to be aimed at it does make more sense.

    IBIS simulation is out of question right now, I lack the knowledge and time to learn how to do it right now. I will add AC coupling to the clock receiving ends according with some documents I have read along the way.

    Still I would appreciate some feedback on the schematics above, just to make sure I did not miss anything important.

     Best Regards.

    Elder.

  • 0 in reply to Elder Costa17
    TI__Genius 9920 points
    Hi Elder,
    Notice CDCM6208 LVDS-like driver is a CML structure with low swing, not a true LVDS driver. That's why datasheet shows those test conditions, just for matching CML driver.
    The Vcm-ac means the bias voltage is only from driver, but Vcm-dc means the bias voltage combined the effect from both driver and loads.
    Your selection AC coupling is safe, and recommended in datasheet.

    Regards,
    Shawn
  • 0 in reply to Shawn Han
    Expert 2825 points

    Hi, Shawn, thank you for your comment.

    What about the schematics in the fourth post above? I would like to make sure I have all the bases covered. In particular, I have powered it with 1.8V as the data sheet makes no distinction on VDD_* regarding performance. I am placing the AC decoupling close to the terminations as shown on another post about CDCUN1208.

    Thank you.

  • 0 in reply to Elder Costa17
    TI__Genius 9920 points
    Hi Elder,
    1， I2C SDA and SCL need pull-up resistors, for example, 1 kOhm to 1.8V supply.
    2， Make sure Input Voltage on pin SDA and SCL is in the range of (-0.5V ~ 2.45V) when DVDD = 1.8 V. (datasheet spec. in 7.3 Recommended Operating Conditions)
    3, If you concern spurs caused by different clock output frequencies, please consider to isolate clock output power supplies (VDD_Y*).
    The same frequency could share one filtered supply path.

    Regards,
    Shawn
  • 0 in reply to Shawn Han
    Expert 2825 points

    Hi, Shawn,

    Thanks for the answers.

    Re 1 and 2, CDCM is already in a 1.8V I2C bus and pull-ups are in another page.

    Re 3, thanks for the hint, I will separate the DVDDs. FWIW frequencies are 5MHz (6 outputs) and 40MHz (2 outputs).

    BR,

    Elder.