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Hello Support,
Can you please tell me how many GCLK Cycles are required for MibSPI RAM Auto-Initialization to complete [ BUFINITACTIVE bit of SPIFLG Register] under WORST CASE timing?
Also, how does one determine that from TRM?
Thank you.
Regards
Pashan
Hello Haixiao,
It is TMS570LS20216.
Also, please let me know which section of TRM I will find that information.
Thank you.
Regards
Pashan
Hello Pashan,
This type of information is typically found in the product datasheet rather than the TRM. SPNS141F is the relevant lit number for the TMS570SL20216. Section 2.3.5 shows the mapping of the auto initialization controls per peripheral SRAM, but this particular version does not show the execution time. I will put in an enhancement ticket asking to include this information.
I believe the auto-init timing is always the same - there is no worst case. It is simply one peripheral clock cycle per word of SRAM implemented. The resulting GCLK cycles would be based on the ratio of GCLK to peripheral clock in your system.
Regards,
Karl
Hello Karl,
Thank you for the exact response.
Please let me know how many clock cycles [VCLK or VCLKA] it takes for DCAN SWR bit to toggle automatically from High State to LOW State at the end of performing software reset?
I am assuming it just clears the DCAN Register set and doesn't clear the DCAN RAM and Parity RAM areas.
Also, if there is a worst case scenario or always constant.
Thank you.
Regards
Pashan
Hi Pashan,
I fear I am not an expert on our peripheral design so I will defer to my colleagues.
Regards,
Karl