Hello.
I made a device based on C5535.
When running through the XDS-100 debugger, everything is fine.
When running with a flush, the C5535 reads the program code, but then does not work. I draw a conclusion about it by GPIO17 IP-Phone_DSP(2x_Channel)(Ver. 1.00).sch
8662.main.c
- it does not work.
/**
* main.c
*/
/* ANSI C headers */
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include "csl_intc.h"
/* System definitions and utilities */
#include <ti/mas/types/types.h>
/* AER, DRC, AGC, MSS and BF header files */
#include <ti/mas/aer/aer.h>
#include <ti/mas/aer/agc.h>
#include <ti/mas/aer/drc.h>
#include <ti/mas/aer/mss.h>
#include <ti/mas/aer/bf.h>
#include "device.h"
/* AER simulation constants and data structures */
#include <ti/mas/aer/test/aersim/aersim.h>
#include <ti/mas/aer/test/aersim/aerbuffs.h>
/* SIU simulation header files */
#include <ti/mas/aer/test/siusim/siu.h>
#include <ti/mas/aer/test/siusim/siuloc.h>
#include <ti/mas/aer/test/siusim/siuaer.h>
#include <ti/mas/aer/test/siusim/siubf.h>
#include <ti/mas/aer/test/piusim/piuloc.h>
#define AER_SIM_PEAK_MIPS_ERLE_THRESH 10
#define AER_SIM_DURATION_CONVERGED 3000 /* Run 30 seconds after converged */
/* Global structures for AER simulation */
siuSetup_t siuSetup; /* simulation setup/configuration structure */
siuInst_t siu_inst; /* system integration unit (SIU) instance structure */
piuInst_t piu_inst; /* PCM interface unit (PIU) instance structure */
aepSimInst_t aepSimInst; /* Acoustic echo path (AEP) simulator structure */
//aersimFileIO_t aersim_fio; /* File I/O structure */
//sgnInstBuf_t sgnTxInst[AER_SIM_NUM_MIC]; /* Signal Generator (SGN) for Tx path (Near End) */
//sgnInstBuf_t sgnRxInst; /* Signal Generator (SGN) for Rx path (Far End) */
/* Input and output buffers for AER simulation */
//linSample sim_data_rx_in [SIU_AER_MAX_FRAME_LENGTH];
linSample sim_data_rx_out [SIU_AER_MAX_FRAME_LENGTH];
linSample sim_data_dac [SIU_AER_MAX_FRAME_LENGTH]; /* signal to D/A */
linSample sim_data_rx_sync [SIU_AER_MAX_FRAME_LENGTH]; /* reference signal */
linSample sim_data_ne_speech[AER_SIM_NUM_MIC][SIU_AER_MAX_FRAME_LENGTH];
linSample sim_data_mic [AER_SIM_NUM_MIC][SIU_AER_MAX_FRAME_LENGTH];
linSample sim_data_tx_in [AER_SIM_NUM_MIC][SIU_AER_MAX_FRAME_LENGTH];
linSample sim_data_tx_out [SIU_AER_MAX_FRAME_LENGTH];
#pragma DATA_ALIGN(bf_null, 4);
linSample bf_null[AER_SIM_NUM_MIC][SIU_AER_MAX_FRAME_LENGTH];
/* Buffers for loading or reading AER tail model coefficients */
#define NUM_H_VEC_GET 3
#define NUM_H_VEC_PUT 3
Fract aer_coef_mant[aer_NUM_WORDS_PER_H_VEC_16K*NUM_H_VEC_PUT];
tint aer_coef_exp[NUM_H_VEC_PUT];
aerTailModel_t aer_tail_model;
/* Buffers for reading BF filter coefficients */
Fract bf_filt_coef[AER_SIM_NUM_BF_MIC][bf_MAX_SUPPORTED_FILT_LEN];
tint bf_filt_len;
/* Prototypes of the funtions only referenced in this file */
//tbool aer_sim_fio_read_fe(aersimFileIO_t *fio, linSample *data_fe);
//tbool aer_sim_fio_read_ne(aersimFileIO_t *fio,
// linSample data_ne[][SIU_AER_MAX_FRAME_LENGTH],tint num_input);
//void aer_sim_fio_write_data(aersimFileIO_t *fio);
tint aer_sim_get_erle(siuInst_t *inst);
void aer_sim_print_version_mips(siuInst_t *inst);
void aer_sim_cfg_on_the_fly(siuInst_t *inst);
/* global variables for debugging purpose - to set conditional breakpoint */
Uint32 frm_cnt = 0;
int my_frm_cnt = 0;
int num_frames_converged = 0;
/******************************************************************************
* FUNCTION PURPOSE: Get ERLE Measurement form AER
*****************************************************************************/
tint aer_sim_get_erle(siuInst_t *inst)
{
aerDebugStat_t aer_dbg;
aerVersion_t aer_ver;
/* get ERLE from the first mic */
aerGetPerformance(inst->aerHFInst[0], &aer_dbg, &aer_ver, FALSE);
return(aer_dbg.max_canc_l2);
} /* aer_sim_get_erle */
/******************************************************************************
* FUNCTION PURPOSE: Simulate real time on-the-fly configuration/control of AER.
*****************************************************************************/
void aer_sim_cfg_on_the_fly(siuInst_t *inst)
{
int i;
tint num_coeff_words, ret_code;
/* Control AER: First, stop the program and change toggle_aer to TRUE. */
if (siuSetup.toggle_aer) { /* --> break point can be set here to stop the code */
/* Second, change aerCtl in Code Composer watch window to configure AER. */
for(i=0; i<inst->phone_sys.num_HF_mic; i++){
aerControl (inst->aerHFInst[i], (aerControl_t *)&siuSetup.aerCtl);
}
siuSetup.toggle_aer = FALSE;
}
/* Control AGC: First, stop the program and change toggle_agc to TRUE. */
if (siuSetup.toggle_agc) { /* --> break point can be set here to stop the code */
/* Second, change agcCtl in Code Composer watch window to configure AGC. */
for(i=0; i<inst->phone_sys.num_HF_mic; i++){
agcControl (inst->agcHFInst[i], (agcControl_t *)&siuSetup.agcCtl);
}
siuSetup.toggle_agc = FALSE;
}
/* Change SIU gains: follow same procedure as above */
if (siuSetup.toggle_siugain) {
for(i=0; i<inst->phone_sys.num_HF_mic; i++){
siuGainControl (inst->agcHFhandles[i], (siuGainControl_t *)&siuSetup.siuGainCtl);
}
siuSetup.toggle_siugain = FALSE;
}
/* Read tail model filter from AER */
if (siuSetup.toggle_getflt) {
if(siuSetup.aer_kernel_srate == AER_SIM_SRATE_16000_DIV_8K) {
num_coeff_words = aer_NUM_WORDS_PER_H_VEC_16K*NUM_H_VEC_GET;
}
else {
num_coeff_words = aer_NUM_WORDS_PER_H_VEC_8K*NUM_H_VEC_GET;
}
ret_code = aerGetFilter(inst->aerHFInst[0], &aer_tail_model, &aer_coef_mant[0],
&aer_coef_exp[0], 0, num_coeff_words);
if(ret_code != aer_NOERR) {
//printf("Error when calling aerGetFilter with error code %d!\n", ret_code);
exit(0);
}
for(i=0; i<siuSetup.system_cfg.num_BF_mic; i++)
{
ret_code = bfGetFilter(inst->bfInst, &bf_filt_coef[i][0], &bf_filt_len, bf_FG_BF, i);
if(ret_code != bf_NOERR) {
//printf("Error when calling bfGetFilter with error code %d!\n", ret_code);
exit(0);
}
}
siuSetup.toggle_getflt = FALSE;
}
/* pre-load AER tail model filter */
if (siuSetup.toggle_putflt) {
if(siuSetup.aer_kernel_srate == AER_SIM_SRATE_16000_DIV_8K) {
num_coeff_words = aer_NUM_WORDS_PER_H_VEC_16K*NUM_H_VEC_PUT;
}
else {
num_coeff_words = aer_NUM_WORDS_PER_H_VEC_8K*NUM_H_VEC_PUT;
}
/* load valid tail model through CCS before executing code below */
ret_code = aerPutFilter(inst->aerHFInst[0], &aer_tail_model, &aer_coef_mant[0],
&aer_coef_exp[0], 0, aer_NUM_WORDS_PER_H_VEC_16K, FALSE);
if(ret_code != aer_NOERR) {
//printf("Error when calling aerPutFilter with error code %d!\n", ret_code);
exit(0);
}
ret_code = aerPutFilter(inst->aerHFInst[0], &aer_tail_model,
&aer_coef_mant[aer_NUM_WORDS_PER_H_VEC_16K],
&aer_coef_exp[0], aer_NUM_WORDS_PER_H_VEC_16K,
aer_NUM_WORDS_PER_H_VEC_16K, FALSE);
if(ret_code != aer_NOERR) {
//printf("Error when calling aerPutFilter with error code %d!\n", ret_code);
exit(0);
}
ret_code = aerPutFilter(inst->aerHFInst[0], &aer_tail_model,
&aer_coef_mant[aer_NUM_WORDS_PER_H_VEC_16K*2],
&aer_coef_exp[0], aer_NUM_WORDS_PER_H_VEC_16K*2,
aer_NUM_WORDS_PER_H_VEC_16K, TRUE);
if(ret_code != aer_NOERR) {
//printf("Error when calling aerPutFilter with error code %d!\n", ret_code);
exit(0);
}
siuSetup.toggle_putflt = FALSE;
}
/* code below can be used to test adaptive AGC
if(frm_cnt == 1000) {
siuSetup.agcCtl.valid_bitfield = agc_CTL_VALID_SAT_THRESHOLD;
siuSetup.agcCtl.sat_threshold = 1024;
agcControl (inst->agcHFInst[0], (agcControl_t *)&siuSetup.agcCtl);
printf("Start filter rescaling test. Reduce AGC saturation threshold.\n");
}
if(frm_cnt == 2000) {
siuSetup.agcCtl.valid_bitfield = agc_CTL_VALID_SAT_THRESHOLD;
siuSetup.agcCtl.sat_threshold = 32500;
agcControl (inst->agcHFInst[0], (agcControl_t *)&siuSetup.agcCtl);
printf("Change AGC saturation threshold back to what it was.\n");
}
*/
} /* aer_sim_cfg_on_the_fly */
/******************************************************************************
* FUNCTION PURPOSE: Print AER version number and measured MIPS.
*****************************************************************************/
void aer_sim_print_version_mips(siuInst_t *inst)
{
aerDebugStat_t aer_dbg;
aerVersion_t aer_ver;
aerGetPerformance(inst->aerHFInst[0], &aer_dbg, &aer_ver, FALSE);
//printf("AER version: %d.%d.%d.%d.%d.%d\n", aer_ver.major, aer_ver.minor,
// aer_ver.patch, aer_ver.build, aer_ver.quality, aer_ver.btype);
if(siuSetup.aer_mips_profile) {
#ifdef ti_targets_C55_large
//printf("C55x: AER Tx Max Cycles = %ld, Avg Cycles = %ld\n",
// siuSetup.TxCyclesMax, siuSetup.TxCyclesAvg);
//printf("C55x: AER Rx Max Cycles = %ld, Avg Cycles = %ld\n",
// siuSetup.RxCyclesMax, siuSetup.RxCyclesAvg);
#else
#ifndef gnu_targets_arm_GCArmv7A/* c64x+ */
printf("C64x+/C674x: AER Tx Max Cycles = %d, Avg Cycles = %d\n",
siuSetup.TxCyclesMax, siuSetup.TxCyclesAvg);
printf("C64x+/C674x: AER Rx Max Cycles = %d, Avg Cycles = %d\n",
siuSetup.RxCyclesMax, siuSetup.RxCyclesAvg);
#endif
#endif
//printf("MIPS measurement done\n");
}
} /* aer_sim_print_version_mips */
CSL_IRQ_Dispatch dispatchTable;
///////////////////////////////////////////////////////////////////////////////
/* -------------------- MAIN SIMULATION FUNCTION --------------------------- */
/////////////////////////////////////////////////////////////////////////////
int main()
{
tint num_mic, mic_type;
DeviceInit();
DeviceStart();
aer_sim_init(&siuSetup);
aer_sim_get_cfg(&siuSetup);
mic_type = siuSetup.system_cfg.mult_mic_type;
if(mic_type == AER_SIM_MIC_TYPE_ARRAY) {
num_mic = siuSetup.system_cfg.num_BF_mic;
}
else {
num_mic = siuSetup.system_cfg.num_HF_mic;
}
aer_sim_apply_config(&siuSetup);
aer_sim_init_siu(&siu_inst, &siuSetup);
aer_sim_init_piu(&piu_inst, &siuSetup);
aer_sim_instantiate_aer(&siu_inst, &siuSetup);
aer_sim_open_aep(&aepSimInst, &siuSetup);
aer_sim_config_aer_params(&siu_inst, &siuSetup);
aer_sim_aep_config(&aepSimInst, &siuSetup.aep_params,
siuSetup.aep_gain_adj_exp, siuSetup.aep_gain_adj_mant);
//aerControl_t aer_ctl;
//***** LOOP ****
loop {
if(flagUART_RX){
flagUART_RX = 0;
UART_params_apply();
}
aer_sim_cfg_on_the_fly(&siu_inst);
frm_cnt++;
if(frm_cnt ==50000)
GPIO_write(hGpio17, CSL_GPIO_PIN14, 1);
if(frm_cnt ==100000){
GPIO_write(hGpio17, CSL_GPIO_PIN14, 0);
frm_cnt = 0;
}
if(F_read_block(fr_bf))
{
if(TRUE)//aer_off_music == 0)
{
siuReceiveIn(&siu_inst, fr_bf, sim_data_rx_out, NULL,
siuSetup.system_cfg.num_HF_mic);
piuReceiveIn(&piu_inst, sim_data_rx_out, sim_data_dac, sim_data_rx_sync);
}
switch(spkr_sel)
{
case 0:
spkr_writeL_block(bf_null[0]);
//spkr_writeR_block(bf_null[0]);
break;
case 1:
if(aer_off_music)
spkr_writeL_block(fr_bf);
else
spkr_writeL_block(sim_data_dac);
break;
case 2:
/*if(aer_off_music)
spkr_writeL_block(fr_bf);
else
spkr_writeR_block(sim_data_dac);*/
break;
}
}
switch(mic_sel)
{
case 0:
if(mic_readL_block(sim_data_ne_speech[0]))
{
//��� ��������� ���������, ������ ������� �����
aer_sim_aep_add_echo(&aepSimInst, sim_data_dac, bf_null,
sim_data_mic, num_mic, 1);
piuSendIn(&piu_inst, sim_data_mic, sim_data_tx_in, num_mic);
siuSendIn(&siu_inst, sim_data_rx_sync, sim_data_tx_in, sim_data_tx_out,
NULL, num_mic, mic_type, siuSetup.aer_sout_frm_size);
F_write_block(sim_data_tx_out);
}
break;
case 1:
if(mic_readR_block(sim_data_ne_speech[0]))
{
//�������� ��������_1 (����� ����� I2S)
aer_sim_aep_add_echo(&aepSimInst, sim_data_dac, sim_data_ne_speech,
sim_data_mic, num_mic, 1);
piuSendIn(&piu_inst, sim_data_mic, sim_data_tx_in, num_mic);
siuSendIn(&siu_inst, sim_data_rx_sync, sim_data_tx_in, sim_data_tx_out,
NULL, num_mic, mic_type, siuSetup.aer_sout_frm_size);
F_write_block(sim_data_tx_out);
}
break;
case 2:
if(mic_readL_block(sim_data_ne_speech[0]))
{
//�������� ��������_2 (������ ����� I2S)
aer_sim_aep_add_echo(&aepSimInst, sim_data_dac, sim_data_ne_speech,
sim_data_mic, num_mic, 1);
piuSendIn(&piu_inst, sim_data_mic, sim_data_tx_in, num_mic);
siuSendIn(&siu_inst, sim_data_rx_sync, sim_data_tx_in, sim_data_tx_out,
NULL, num_mic, mic_type, siuSetup.aer_sout_frm_size);
F_write_block(sim_data_tx_out);
}
break;
}
}
return(0);
}
//*****************************************************************************
// DeviceInit
//*****************************************************************************
void DeviceInit()
{
PLL_Obj pllObj;
PLL_Config *configInfo;
PLL_Handle hPll;
Uint32 pllInstId;
int i;
Uint16 prcr;
CSL_SYSCTRL_REGS->PCGCR1 = 0x0000;
CSL_SYSCTRL_REGS->PCGCR2 = 0x0000;
IRQ_init(&dispatchTable, 0);
IRQ_globalDisable();
IRQ_disableAll();
IRQ_clearAll();
IRQ_setVecs((Uint32)&VECSTART);
// Set PLL
const PLL_Config pllCfg_100MHz = {0x8C31, 0x0173, 0x0806, 0x0000}; //from 12MHz
pllInstId = 0;
PLL_init(&pllObj,pllInstId);
hPll = &pllObj;
PLL_reset(hPll);
configInfo = (PLL_Config *)&pllCfg_100MHz;
PLL_config(hPll, configInfo);
for(i=0;i<100;i++);
PLL_enable(hPll);
for(i=0;i<100;i++);
//Set PinMap
CSL_FINST(CSL_SYSCTRL_REGS->EBSR, SYS_EBSR_PPMODE, MODE1);
CSL_FINST(CSL_SYSCTRL_REGS->EBSR, SYS_EBSR_SP1MODE, MODE0);
CSL_FINST(CSL_SYSCTRL_REGS->EBSR, SYS_EBSR_SP0MODE, MODE1);
// Enable HWA, CPU, DPORT, MPORT, XPORT, and IPORT in ICR */
*(volatile ioport Uint16 *)(0x0001) = 0x000E;
/* Execute idle instruction */
asm(" idle");
//Enable peripherals
CSL_SYSCTRL_REGS->PCGCR1 = 0x1c02;
CSL_SYSCTRL_REGS->PCGCR2 = 0x0003;
// Reset all peripherals
CSL_SYSCTRL_REGS->PSRCR = 0x0020;
CSL_SYSCTRL_REGS->PRCR = 0x00BB;
do
{
prcr = CSL_SYSCTRL_REGS->PRCR;
} while (prcr != 0);
}
//---------------------------------------------------------------
void DeviceStart()
{
int i, a;
for(i=0; i<FRAME_LENGTH*2; i++){
bufN_WL[i] = 0;
bufN_WR[i] = 0;
bufN_RL[i] = 0;
bufN_RR[i] = 0;
bufF_W[i] = 0;
bufF_R[i] = 0;
}
for(a=0; a<AER_SIM_NUM_MIC; a++)
for(i=0; i<SIU_AER_MAX_FRAME_LENGTH; i++)
bf_null[a][i] = 0x0;
for(i=0; i<100; i++)
bufUART[i] = 0;
GPIO_init();
GPIO_write(hGpio17, CSL_GPIO_PIN17, 1);// ����� AIC
Wait(100000);
i2c_init();
Wait(300);
UARTinit();
DmaInit();
I2sDmaF_init();
I2sDmaN_init();
i2sF_init();
i2sN_init();
aic_init();
IRQ_globalEnable();
}
//****************************************************************************
// GPIO_init();
//****************************************************************************
void GPIO_init()
{
CSL_Status status;
CSL_GpioPinConfig config;
// Make Serial port 0 and 1, parallel port's 8 pin and
// A15 to A20 pin as GPIO
//
//CSL_FINST(CSL_SYSCTRL_REGS->EBSR, SYS_EBSR_SP0MODE, MODE2);
// Open GPIO module
//hGpio12 = GPIO_open(&gpioObj12, &status);
//hGpio13 = GPIO_open(&gpioObj13, &status);
hGpio14 = GPIO_open(&gpioObj14, &status);
//hGpio16 = GPIO_open(&gpioObj16, &status);
hGpio17 = GPIO_open(&gpioObj17, &status);
// Configure GPIO
/* config.pinNum = CSL_GPIO_PIN12;
config.direction = CSL_GPIO_DIR_OUTPUT;
config.trigger = CSL_GPIO_TRIG_CLEAR_EDGE;
GPIO_configBit(hGpio12, &config);
config.pinNum = CSL_GPIO_PIN13;
config.direction = CSL_GPIO_DIR_OUTPUT;
config.trigger = CSL_GPIO_TRIG_CLEAR_EDGE;
GPIO_configBit(hGpio13, &config);
*/
config.pinNum = CSL_GPIO_PIN14;
config.direction = CSL_GPIO_DIR_OUTPUT;
config.trigger = CSL_GPIO_TRIG_CLEAR_EDGE;
GPIO_configBit(hGpio14, &config);
/* config.pinNum = CSL_GPIO_PIN16;
config.direction = CSL_GPIO_DIR_OUTPUT;
config.trigger = CSL_GPIO_TRIG_CLEAR_EDGE;
GPIO_configBit(hGpio16, &config);
*/
config.pinNum = CSL_GPIO_PIN17;
config.direction = CSL_GPIO_DIR_OUTPUT;
config.trigger = CSL_GPIO_TRIG_CLEAR_EDGE;
GPIO_configBit(hGpio17, &config);
int i;
// Write 1 to output pin
// GPIO_write(hGpio12, CSL_GPIO_PIN12, 1);
// GPIO_write(hGpio13, CSL_GPIO_PIN13, 1);
// GPIO_write(hGpio14, CSL_GPIO_PIN14, 1);
// GPIO_write(hGpio16, CSL_GPIO_PIN16, 1);*/
GPIO_write(hGpio17, CSL_GPIO_PIN17, 1);
Wait(10000);
// GPIO_write(hGpio12, CSL_GPIO_PIN12, 0);
// GPIO_write(hGpio13, CSL_GPIO_PIN13, 0);
// GPIO_write(hGpio14, CSL_GPIO_PIN14, 0);
// GPIO_write(hGpio16, CSL_GPIO_PIN16, 0);*/
GPIO_write(hGpio17, CSL_GPIO_PIN17, 0);
Wait(10000);
}
//*****************************************************************************
// DmaInit
// Description: Initializes DMA, enables DMA interrupts
//*****************************************************************************
void DmaInit()
{
Uint16 ifrValue;
IRQ_disable(DMA_EVENT);
IRQ_clear(DMA_EVENT);
CSL_SYSCTRL_REGS->DMAIER = 0x0000;// Disable DMA interrupts
ifrValue = CSL_SYSCTRL_REGS->DMAIFR;// Clear pending DMA interrupts
CSL_SYSCTRL_REGS->DMAIFR |= ifrValue;
IRQ_plug(DMA_EVENT, &DmaIsr);
IRQ_enable(DMA_EVENT);
DMA_init();
}
//-----------------------------------------------------------------------------
//*****************************************************************************
// void i2s_init()
//****************************************************************************
void i2sN_init()
{
CSL_I2sHandle hI2sN;
I2S_Config hwConfig;
// Open the device with instance 2
hI2sN = I2S_open(I2S_INSTANCE2, DMA_INTERRUPT, I2S_CHAN_STEREO);
// Set the value for the configure structure
hwConfig.dataType = I2S_STEREO_ENABLE;
hwConfig.loopBackMode = I2S_LOOPBACK_DISABLE;
hwConfig.fsPol = I2S_FSPOL_LOW;
hwConfig.clkPol = I2S_RISING_EDGE;
hwConfig.datadelay = I2S_DATADELAY_ONEBIT;
hwConfig.datapack = I2S_DATAPACK_ENABLE;
hwConfig.signext = I2S_SIGNEXT_DISABLE;
hwConfig.wordLen = I2S_WORDLEN_16;
hwConfig.i2sMode = I2S_SLAVE;
hwConfig.FError = I2S_FSERROR_DISABLE;
hwConfig.OuError = I2S_OUERROR_DISABLE;
hwConfig.clkDiv = I2S_CLKDIV128;
hwConfig.dataFormat = I2S_DATAFORMAT_DSP;
hwConfig.fsDiv = I2S_FSDIV32;
// Configure hardware registers
I2S_setup(hI2sN, &hwConfig);
I2S_transEnable(hI2sN, TRUE);
hI2sN->firstRead = FALSE;
}
//-----------------------------------------------------------------------------
void i2sF_init()
{
CSL_I2sHandle hI2sF;
I2S_Config hwConfig;
/* Open the device with instance 2 */
hI2sF = I2S_open(I2S_INSTANCE0, DMA_INTERRUPT, I2S_CHAN_STEREO);
/* Set the value for the configure structure */
hwConfig.dataType = I2S_STEREO_ENABLE;
hwConfig.loopBackMode = I2S_LOOPBACK_DISABLE;
hwConfig.fsPol = I2S_FSPOL_LOW;
hwConfig.clkPol = I2S_RISING_EDGE;
hwConfig.datadelay = I2S_DATADELAY_ONEBIT;
hwConfig.datapack = I2S_DATAPACK_ENABLE;
hwConfig.signext = I2S_SIGNEXT_DISABLE;
hwConfig.wordLen = I2S_WORDLEN_16;
hwConfig.i2sMode = I2S_SLAVE;
hwConfig.FError = I2S_FSERROR_ENABLE;
hwConfig.OuError = I2S_OUERROR_ENABLE;
hwConfig.clkDiv = I2S_CLKDIV16;
hwConfig.dataFormat = I2S_DATAFORMAT_DSP;
hwConfig.fsDiv = I2S_FSDIV16;
/* Configure hardware registers */
I2S_setup(hI2sF, &hwConfig);
I2S_transEnable(hI2sF, TRUE);
hI2sF->firstRead = FALSE;
}
//*****************************************************************************
// I2sDmaInit
// Configures and starts I2S with DMA
//*****************************************************************************
void I2sDmaN_init()
{
CSL_DMA_Config dmaConfig;
CSL_Status status;
// Configure DMA ch4 for I2S write left
dmaConfig.pingPongMode = CSL_DMA_PING_PONG_ENABLE;
dmaConfig.autoMode = CSL_DMA_AUTORELOAD_ENABLE;
dmaConfig.burstLen = CSL_DMA_TXBURST_1WORD;
dmaConfig.trigger = CSL_DMA_EVENT_TRIGGER;
dmaConfig.dmaEvt = CSL_DMA_EVT_I2S2_TX;
dmaConfig.dmaInt = CSL_DMA_INTERRUPT_ENABLE;
dmaConfig.chanDir = CSL_DMA_WRITE;
dmaConfig.trfType = CSL_DMA_TRANSFER_IO_MEMORY;
dmaConfig.dataLen = FRAME_LENGTH*4; // two frames
dmaConfig.srcAddr = (Uint32)bufN_WLPi;
dmaConfig.destAddr = (Uint32)&CSL_I2S2_REGS->I2STXLT0;
dmaNLTxHandle = DMA_open(DMA_NL_CHAN_TX, &dmaObj0,&status);
status = DMA_config(dmaNLTxHandle, &dmaConfig);
DMA_start (dmaNLTxHandle);
/* // Configure DMA ch5 for I2S write right
dmaConfig.pingPongMode = CSL_DMA_PING_PONG_ENABLE;
dmaConfig.autoMode = CSL_DMA_AUTORELOAD_ENABLE;
dmaConfig.burstLen = CSL_DMA_TXBURST_1WORD;
dmaConfig.trigger = CSL_DMA_EVENT_TRIGGER;
dmaConfig.dmaEvt = CSL_DMA_EVT_I2S2_TX;
dmaConfig.dmaInt = CSL_DMA_INTERRUPT_ENABLE;
dmaConfig.chanDir = CSL_DMA_WRITE;
dmaConfig.trfType = CSL_DMA_TRANSFER_IO_MEMORY;
dmaConfig.dataLen = FRAME_LENGTH*4; // two frames
dmaConfig.srcAddr = (Uint32)bufN_WRPi;
dmaConfig.destAddr = (Uint32)&CSL_I2S2_REGS->I2STXRT0;
dmaNRTxHandle = DMA_open(DMA_NR_CHAN_TX, &dmaObj4,&status);
status = DMA_config(dmaNRTxHandle, &dmaConfig);
DMA_start (dmaNRTxHandle);
*/
// Configure DMA ch6 for I2S left read
dmaConfig.pingPongMode = CSL_DMA_PING_PONG_ENABLE;
dmaConfig.autoMode = CSL_DMA_AUTORELOAD_ENABLE;
dmaConfig.burstLen = CSL_DMA_TXBURST_1WORD;
dmaConfig.trigger = CSL_DMA_EVENT_TRIGGER;
dmaConfig.dmaEvt = CSL_DMA_EVT_I2S2_RX;
dmaConfig.dmaInt = CSL_DMA_INTERRUPT_ENABLE;
dmaConfig.chanDir = CSL_DMA_READ;
dmaConfig.trfType = CSL_DMA_TRANSFER_IO_MEMORY;
dmaConfig.dataLen = FRAME_LENGTH*4; // two frames
dmaConfig.srcAddr = (Uint32)&CSL_I2S2_REGS->I2SRXLT0;
dmaConfig.destAddr = (Uint32)bufN_RLPi;
dmaNLRxHandle = DMA_open(DMA_NL_CHAN_RX, &dmaObj1,&status);
DMA_config(dmaNLRxHandle, &dmaConfig);
DMA_start (dmaNLRxHandle);
// Configure DMA ch7 for I2S right read
dmaConfig.pingPongMode = CSL_DMA_PING_PONG_ENABLE;
dmaConfig.autoMode = CSL_DMA_AUTORELOAD_ENABLE;
dmaConfig.burstLen = CSL_DMA_TXBURST_1WORD;
dmaConfig.trigger = CSL_DMA_EVENT_TRIGGER;
dmaConfig.dmaEvt = CSL_DMA_EVT_I2S2_RX;
dmaConfig.dmaInt = CSL_DMA_INTERRUPT_ENABLE;
dmaConfig.chanDir = CSL_DMA_READ;
dmaConfig.trfType = CSL_DMA_TRANSFER_IO_MEMORY;
dmaConfig.dataLen = FRAME_LENGTH*4; // two frames
dmaConfig.srcAddr = (Uint32)&CSL_I2S2_REGS->I2SRXRT0;
dmaConfig.destAddr = (Uint32)bufN_RRPi;
dmaNRRxHandle = DMA_open(DMA_NR_CHAN_RX, &dmaObj5,&status);
DMA_config(dmaNRRxHandle, &dmaConfig);
DMA_start (dmaNRRxHandle);
flagN_RLI = 0;
flagN_RRI = 0;
flagN_WLI = 0;
flagN_WRI = 0;
}
//------------------------------------------------------------------
void I2sDmaF_init()
{
CSL_DMA_Config dmaConfig;
CSL_Status status;
// Configure DMA ch0 for I2S write
dmaConfig.pingPongMode = CSL_DMA_PING_PONG_ENABLE;
dmaConfig.autoMode = CSL_DMA_AUTORELOAD_ENABLE;
dmaConfig.burstLen = CSL_DMA_TXBURST_1WORD;
dmaConfig.trigger = CSL_DMA_EVENT_TRIGGER;
dmaConfig.dmaEvt = CSL_DMA_EVT_I2S0_TX;
dmaConfig.dmaInt = CSL_DMA_INTERRUPT_ENABLE;
dmaConfig.chanDir = CSL_DMA_WRITE;
dmaConfig.trfType = CSL_DMA_TRANSFER_IO_MEMORY;
dmaConfig.dataLen = FRAME_LENGTH*4; // two frames
dmaConfig.srcAddr = (Uint32)bufF_WPi;
dmaConfig.destAddr = (Uint32)&CSL_I2S0_REGS->I2STXLT0;
dmaFTxHandle = DMA_open(DMA_F_CHAN_TX, &dmaObj2,&status);
status = DMA_config(dmaFTxHandle, &dmaConfig);
DMA_start (dmaFTxHandle);
// Configure DMA ch2 for I2S read
dmaConfig.pingPongMode = CSL_DMA_PING_PONG_ENABLE;
dmaConfig.autoMode = CSL_DMA_AUTORELOAD_ENABLE;
dmaConfig.burstLen = CSL_DMA_TXBURST_1WORD;
dmaConfig.trigger = CSL_DMA_EVENT_TRIGGER;
dmaConfig.dmaEvt = CSL_DMA_EVT_I2S0_RX;
dmaConfig.dmaInt = CSL_DMA_INTERRUPT_ENABLE;
dmaConfig.chanDir = CSL_DMA_READ;
dmaConfig.trfType = CSL_DMA_TRANSFER_IO_MEMORY;
dmaConfig.dataLen = FRAME_LENGTH*4; // two frames
dmaConfig.srcAddr = (Uint32)&CSL_I2S0_REGS->I2SRXLT0;
dmaConfig.destAddr = (Uint32)bufF_RPi;
dmaFRxHandle = DMA_open(DMA_F_CHAN_RX, &dmaObj3,&status);
DMA_config(dmaFRxHandle, &dmaConfig);
DMA_start (dmaFRxHandle);
flagF_RI = 0;
flagF_WI = 0;
}
//------------------------------------------------------------------
//*****************************************************************
// Iterupt DMA
//*****************************************************************
interrupt void DmaIsr(void)
{
CSL_Status status;
volatile Uint16 ifrValue;
Uint16 gp;
// Clear the DMA interrupt
ifrValue = CSL_SYSCTRL_REGS->DMAIFR;
CSL_SYSCTRL_REGS->DMAIFR |= ifrValue;
//Ch 0 Write to ������� �����
if (ifrValue & (1<<0)){
flagF_WI = 1;
if(DMA_getLastTransferType (dmaFTxHandle, &status)){
flagF_WPP = 0;
}
else{
flagF_WPP = 1;
}
}
//Ch 2 Read from ������� �����
if (ifrValue & (1<<2)){
flagF_RI = 1;
if(DMA_getLastTransferType (dmaFRxHandle, &status)){
flagF_RPP = 0;
}
else{
flagF_RPP = 1;
}
}
//Ch 4 Write to left SPKR
if (ifrValue & (1<<4)){
flagN_WLI = 1;
if(DMA_getLastTransferType (dmaNLTxHandle, &status)){
flagN_WLPP = 0;
}
else{
flagN_WLPP = 1;
}
}
/* //Ch 5 Write to right SPKR
if (ifrValue & (1<<5)){
flagN_WRI = 1;
if(DMA_getLastTransferType (dmaNRTxHandle, &status)){
flagN_WRPP = 0;
}
else{
flagN_WRPP = 1;
}
}
*/
//Ch 6 Read from left MIC
if (ifrValue & (1<<6)){
flagN_RLI = 1;
if(DMA_getLastTransferType (dmaNLRxHandle, &status)){
flagN_RLPP = 0;
}
else{
flagN_RLPP = 1;
}
}
//Ch 7 Read from right MIC
if (ifrValue & (1<<6)){
flagN_RRI = 1;
if(DMA_getLastTransferType (dmaNRRxHandle, &status)){
flagN_RRPP = 0;
}
else{
flagN_RRPP = 1;
}
}
}
//-------------------------------------------------------------------------------
Bool mic_readL_block(int* buffer)
{
int i;
Uint32* bL = (Uint32*)buffer;
Uint32* dma;
if(flagN_RLI)
flagN_RLI = 0;
else
return FALSE;
if(flagN_RLPP == 1){
dma = (Uint32*)(&bufN_RL[0]);
for (i = 0; i < FRAME_LENGTH/2; i++)
*bL++ = *dma++;
}
else{
dma = (Uint32*)(&bufN_RL[FRAME_LENGTH]);
for (i = 0; i < FRAME_LENGTH/2; i++)
*bL++ = *dma++;
}
return TRUE;
}
//------------------------------------------------------------------
Bool mic_readR_block(int* buffer)
{
int i;
Uint32* bL = (Uint32*)buffer;
Uint32* dma;
if(flagN_RRI)
flagN_RRI = 0;
else
return FALSE;
if(flagN_RRPP == 1){
dma = (Uint32*)(&bufN_RR[0]);
for (i = 0; i < FRAME_LENGTH/2; i++)
*bL++ = *dma++;
}
else{
dma = (Uint32*)(&bufN_RR[FRAME_LENGTH]);
for (i = 0; i < FRAME_LENGTH/2; i++)
*bL++ = *dma++;
}
return TRUE;
}
//------------------------------------------------------------------
Bool spkr_writeL_block(int* buffer)
{
int i;
Uint32* bL = (Uint32*)buffer;
Uint32* dma;
//while(flagN_WI == 0);
//flagN_WI = 0;
if(flagN_WLI)
flagN_WLI = 0;
else
return FALSE;
if(flagN_WLPP == 1){
dma = (Uint32*)(&bufN_WL[0]);
for (i = 0; i < FRAME_LENGTH/2; i++)
*dma++ = *bL++;
}
else {
dma = (Uint32*)(&bufN_WL[FRAME_LENGTH]);
for (i = 0; i < FRAME_LENGTH/2; i++)
*dma++ = *bL++;
}
return TRUE;
}
//-------------------------------------------------------------------------
Bool spkr_writeR_block(int* buffer)
{
int i;
Uint32* bL = (Uint32*)buffer;
Uint32* dma;
//while(flagN_WI == 0);
//flagN_WI = 0;
if(flagN_WRI)
flagN_WRI = 0;
else
return FALSE;
if(flagN_WRPP == 1){
dma = (Uint32*)(&bufN_WR[0]);
for (i = 0; i < FRAME_LENGTH/2; i++)
*dma++ = *bL++;
}
else {
dma = (Uint32*)(&bufN_WR[FRAME_LENGTH]);
for (i = 0; i < FRAME_LENGTH/2; i++)
*dma++ = *bL++;
}
return TRUE;
}
//-------------------------------------------------------------------------
Bool F_read_block(int* buffer)
{
int i;
Uint32* bL = (Uint32*)buffer;
Uint32* dma;
//while(flagF_RI == 0);
//flagF_RI = 0;
if(flagF_RI)
flagF_RI = 0;
else
return FALSE;
if(flagF_RPP == 1){
dma = (Uint32*)(&bufF_R[0]);
for (i = 0; i < FRAME_LENGTH/2; i++)
*bL++ = *dma++;
}
else{
dma = (Uint32*)(&bufF_R[FRAME_LENGTH]);
for (i = 0; i < FRAME_LENGTH/2; i++)
*bL++ = *dma++;
}
return TRUE;
}
//------------------------------------------------------------------
Bool F_write_block(int* buffer)
{
int i;
Uint32* bL = (Uint32*)buffer;
Uint32* dma;
//while(flagF_WI == 0);
//flagF_WI = 0;
if(flagF_WI)
flagF_WI = 0;
else
return FALSE;
if(flagF_WPP == 1){
dma = (Uint32*)(&bufF_W[0]);
for (i = 0; i < FRAME_LENGTH/2; i++)
*dma++ = *bL++;
}
else {
dma = (Uint32*)(&bufF_W[FRAME_LENGTH]);
for (i = 0; i < FRAME_LENGTH/2; i++)
*dma++ = *bL++;
}
return TRUE;
}
//-------------------------------------------------------------------------
//*************************************************************************
//I2C Init
//*************************************************************************
void i2c_init()
{
volatile Uint16 looper;
volatile Uint32 csl_i2c_sys_clk;
// Initialize I2C module
I2C_init(CSL_I2C0);
csl_i2c_sys_clk = GetSysClk()/1000;
// Setup I2C module
i2cSetup.addrMode = CSL_I2C_ADDR_7BIT;
i2cSetup.bitCount = CSL_I2C_BC_8BITS;
i2cSetup.loopBack = CSL_I2C_LOOPBACK_DISABLE;
i2cSetup.freeMode = CSL_I2C_FREEMODE_DISABLE;
i2cSetup.repeatMode = CSL_I2C_REPEATMODE_DISABLE;
i2cSetup.ownAddr = CSL_I2C_OWN_ADDR;
//sysclk to i2c, before pre-scaling
i2cSetup.sysInputClk = csl_i2c_sys_clk/1000u;
//actual i2c serial clk
i2cSetup.i2cBusFreq = CSL_I2C_BUS_FREQ;
startStop = ((CSL_I2C_START) | (CSL_I2C_STOP));
I2C_setup(&i2cSetup);
}
//-----------------------------------------------------------------
Uint32 GetSysClk()
{
Bool pllRDBypass;
Bool pllOutDiv;
Uint32 sysClk;
Uint16 pllM;
Uint16 pllRD;
Uint16 pllOD;
pllM = CSL_FEXT(CSL_SYSCTRL_REGS->CGCR1, SYS_CGCR1_M);
pllRD = CSL_FEXT(CSL_SYSCTRL_REGS->CGCR2, SYS_CGCR2_RDRATIO);
pllOD = CSL_FEXT(CSL_SYSCTRL_REGS->CGCR4, SYS_CGCR4_ODRATIO);
pllRDBypass = CSL_FEXT(CSL_SYSCTRL_REGS->CGCR2, SYS_CGCR2_RDBYPASS);
pllOutDiv = CSL_FEXT(CSL_SYSCTRL_REGS->CGCR4, SYS_CGCR4_OUTDIVEN);
sysClk = 12000000u;//12MHz
if (0 == pllRDBypass)
{
sysClk = sysClk/(pllRD + 4);
}
sysClk = (sysClk * (pllM + 4));
if (1 == pllOutDiv)
{
sysClk = sysClk/(pllOD + 1);
}
// Return the value of system clock in KHz
return(sysClk);
}
//-------------------------------------------------------------------------
//*************************************************************************
// AIC Init
//************************************************************************
Int16 AIC3204_rget( Uint16 regnum, Uint16* regval )
{
Uint16 val[1];
regnum = (regnum & 0x00FF);
Uint16 startStop = ((CSL_I2C_START) | (CSL_I2C_STOP));
I2C_read(val, 1, AIC3204_I2C_ADDR, ®num, 1, TRUE, startStop,
CSL_I2C_MAX_TIMEOUT, FALSE);
Wait(1000);
*regval = val[0];
return val[0];
}
//--------------------------------------------------------------------------
void AIC3204_rset( Uint16 regnum, Uint16 regval )
{
Uint16 cmd[2];
cmd[0] = (regnum & 0x00FF); // 7-bit Device Register
cmd[1] = (regval & 0x00FF); // 8-bit Register Data
Uint16 startStop = ((CSL_I2C_START) | (CSL_I2C_STOP));
I2C_write(cmd, 2, AIC3204_I2C_ADDR, TRUE, startStop,
CSL_I2C_MAX_TIMEOUT);
Wait(1000);
}
//****************************************************************************
//AIC init
//****************************************************************************
void aic_init()
{
Uint16 regval = 0;
// Configure AIC3204
AIC3204_rset( 0, 0x00 ); // Select page 0
AIC3204_rset( 1, 0x01 ); // Reset codec
Wait(1000); // Wait 1ms after reset
AIC3204_rset( 0, 0x01 ); // Select page 1
AIC3204_rset( 1, 0x08 ); // Disable crude AVDD generation from DVDD
AIC3204_rset( 2, 0x01 ); // Enable Analog Blocks, use LDO power
AIC3204_rset( 123,0x05 ); // Force reference to power up in 40ms
Wait(50000); // Wait at least 40ms
AIC3204_rset( 0, 0x00 ); // Select page 0
// PLL and Clocks config and Power Up
if(AIC_SAMPLE_SIZE == 32)
AIC3204_rset( 27, 0x3d ); // BCLK and WCLK are set as o/p; AIC3204(Master); 32-bit sample
else
AIC3204_rset( 27, 0x0d ); // BCLK and WCLK are set as o/p; AIC3204(Master); 16-bit sample
AIC3204_rget(27, ®val);
AIC3204_rset( 28, 0x00 ); // Data ofset = 0
//Reg.4 �������� 3 - clock ������ ������� (MCLK=12���), �� ���� �������� PLLCLK ���������� �� PLL. For MASTER
AIC3204_rset( 4, 0x03 ); // PLL setting: PLLCLK <- MCLK, CODEC_CLKIN <-PLL CLK.
AIC3204_rget(4, ®val);
//Reg.4 �������� 7 - clock ������� �� I2S (BCLK=32���), �� ���� �������� PLLCLK ��������� �� PLL. For SLAVE
//AIC3204_rset( 4, 0x07 ); // PLL setting: PLLCLK <- BCLK, CODEC_CLKIN <-PLL CLK.
//������������� PLL = 7,168. ����� ������� ������� CODEC_CLK = BCLK*PLL = 1,024��� * 48 * 2 = 98.304.000 For SLAVE
/*AIC3204_rset( 5, 0x92 ); // PLL setting: Power up PLL, P=1 and R=2
AIC3204_rset( 6, 0x30 ); // PLL setting: J=48
AIC3204_rset( 7, 0x00 ); // PLL setting: HI_BYTE(D=0)
AIC3204_rset( 8, 0x00 ); // PLL setting: LO_BYTE(D=0)*/
AIC3204_rset( 30, 0x88 ); // For 32 bit clocks per frame in Master mode ONLY
// BCLK=DAC_CLK/N =(12288000/8) = 1.536MHz = 32*fs
Wait(10000); // Wait for PLL to come up
/* // For MASTER
// 32��� (16bit)
//������������� PLL = 7,168. ����� ������� ������� CODEC_CLK = MCLK*PLL = 12��� * 7,168 = 86.016.000 For MASTER
AIC3204_rset( 5, 0x91 ); // PLL setting: Power up PLL, P=1 and R=1
AIC3204_rset( 6, 0x07 ); // PLL setting: J=7
AIC3204_rset( 7, 0x06 ); // PLL setting: HI_BYTE(D=1680)
AIC3204_rset( 8, 0x90 ); // PLL setting: LO_BYTE(D=1680)
//��������� DOSR, NDAC, MADC ��� ����� FS(32���) ��������� �� CODEC_CLK (FS*DOSR*MDAC*NDAC = CODEC_CLK) For MASTER
//CODEC_CLK = MCLK*PLL = 12��� * 7,168 = 86.016.000 = 32��� * 192 * 7 * 2
//��������� ������ � �������� NDAC � NADC ������ �� ����������� ������� ������ (���. 76)
AIC3204_rset( 13, 0x00 ); // Hi_Byte(DOSR) for DOSR = 192 decimal or 0x00�0 DAC oversamppling
AIC3204_rset( 14, 0xC0 ); // Lo_Byte(DOSR) for DOSR = 192 decimal or 0x00�0
AIC3204_rset( 20, 0x80 ); // AOSR for AOSR = 128 decimal or 0x0080 for decimation filters 1 to 6
AIC3204_rset( 11, 0x82 ); // Power up NDAC and set NDAC value to 2 (32���)
AIC3204_rset( 12, 0x87 ); // Power up MDAC and set MDAC value to 7
AIC3204_rset( 18, 0x87 ); // Power up NADC and set NADC value to 7
AIC3204_rset( 19, 0x82 ); // Power up MADC and set MADC value to 2 (32���)
// 24��� (16bit)
//CODEC_CLK = MCLK*PLL = 12��� * 7,168 = 86.016.000 = 24��� * 128 * 7 * 4
AIC3204_rset( 13, 0x00 ); // Hi_Byte(DOSR) for DOSR = 128 decimal or 0x00�0 DAC oversamppling
AIC3204_rset( 14, 0x80 ); // Lo_Byte(DOSR) for DOSR = 128 decimal or 0x00�0
AIC3204_rset( 20, 0x80 ); // AOSR for AOSR = 128 decimal or 0x0080 for decimation filters 1 to 6
AIC3204_rset( 11, 0x84 ); // Power up NDAC and set NDAC value to 4 (24���,16bit)
AIC3204_rset( 12, 0x87 ); // Power up MDAC and set MDAC value to 7
AIC3204_rset( 18, 0x87 ); // Power up NADC and set NADC value to 7
AIC3204_rset( 19, 0x84 ); // Power up MADC and set MADC value to 4 (24���,16bit)
*/
// 22��� (16bit)
//������������� PLL = 7,168. ����� ������� ������� CODEC_CLK = MCLK*PLL = 12��� * 7,168 = 86.016.000 For MASTER
AIC3204_rset( 5, 0x91 ); // PLL setting: Power up PLL, P=1 and R=1
AIC3204_rset( 6, 0x07 ); // PLL setting: J=7
AIC3204_rset( 7, 0x02 ); // PLL setting: HI_BYTE(D=0560)
AIC3204_rset( 8, 0x30 ); // PLL setting: LO_BYTE(D=0560)
//CODEC_CLK = MCLK*PLL = 12��� * 7,056 = 86.016.000 = 22,05��� * 192 * 5 * 4
AIC3204_rset( 13, 0x00 ); // Hi_Byte(DOSR) for DOSR = 192 decimal or 0x00�0 DAC oversamppling
AIC3204_rset( 14, 0xC0 ); // Lo_Byte(DOSR) for DOSR = 192 decimal or 0x00�0
AIC3204_rset( 20, 0x80 ); // AOSR for AOSR = 128 decimal or 0x0080 for decimation filters 1 to 6
AIC3204_rset( 11, 0x84 ); // Power up NDAC and set NDAC value to 4 (24���,16bit)
AIC3204_rset( 12, 0x85 ); // Power up MDAC and set MDAC value to 7
AIC3204_rset( 18, 0x85 ); // Power up NADC and set NADC value to 7
AIC3204_rset( 19, 0x84 ); // Power up MADC and set MADC value to 4 (24���,16bit)
// For SLAVE
// 32��� (16bit)
//���������� DOSR, NDAC, MADC ��� ����� FS(32���) ��������� �� CODEC_CLK (FS*DOSR*MDAC*NDAC = CODEC_CLK)
//CODEC_CLK = BCLK*PLL = (32���*32) * (48,0 * 2) = 98.304.000 = 32��� * 128 * 8 * 3
//��������� ������ � �������� NDAC � NADC ������ �� ����������� ������� ������ (���. 76)
/* AIC3204_rset( 13, 0x00 ); // Hi_Byte(DOSR) for DOSR = 128 decimal or 0x0080 DAC oversamppling
AIC3204_rset( 14, 0x80 ); // Lo_Byte(DOSR) for DOSR = 128 decimal or 0x0080
AIC3204_rset( 20, 0x80 ); // AOSR for AOSR = 128 decimal or 0x0080 for decimation filters 1 to 6
AIC3204_rset( 11, 0x83 ); // Power up NDAC and set NDAC value to 3
AIC3204_rset( 12, 0x88 ); // Power up MDAC and set MDAC value to 8
AIC3204_rset( 18, 0x88 ); // Power up NADC and set NADC value to 8
AIC3204_rset( 19, 0x83 ); // Power up MADC and set MADC value to 3
*/
// DAC ROUTING and Power Up
AIC3204_rset( 0, 0x01 ); // Select page 1
AIC3204_rset( 12, 0x08 ); // LDAC AFIR routed to HPL
AIC3204_rset( 13, 0x08 ); // RDAC AFIR routed to HPR
AIC3204_rset( 0, 0x00 ); // Select page 0
AIC3204_rset( 64, 0x02 ); // Left vol=right vol
AIC3204_rset( 65, 0x00 ); // Left DAC gain to 0dB VOL; Right tracks Left
AIC3204_rset( 63, 0xd4 ); // Power up left,right data paths and set channel
AIC3204_rset( 0, 0x01 ); // Select page 1
AIC3204_rset( 16, 0x00 ); // Unmute HPL , 0dB gain
AIC3204_rset( 17, 0x00 ); // Unmute HPR , 0dB gain
AIC3204_rset( 9 , 0x30 ); // Power up HPL,HPR
Wait(100 ); // Wait
// ADC ROUTING and Power Up
AIC3204_rset( 0, 0x01 ); // Select page 1
AIC3204_rset( 51, 0x48); // power up MICBIAS with AVDD (0x40)or LDOIN 3.3V (0x78) or 1.2V (0x48)//MM - added micbias
AIC3204_rset( 52, 0x0C); //IN3L -> Left Positive, 40k
AIC3204_rset( 54, 0x0C); //IN3R -> Left Negative, 40k
AIC3204_rset( 55, 0xC0); //IN1R -> Right Positive, 40k
AIC3204_rset( 57, 0x30); //IN1L -> Right Negative, 40k
/*
AIC3204_rset( 52, 0x30 ); // IN2L is routed to Left Positive MICPGA with 40k resistance
AIC3204_rset( 54, 0x03 ); // CM is routed to Left Negative MICPGA via CM2L with 40k resistance
AIC3204_rset( 55, 0x30 ); // IN2R is routed to Right Positive MICPGA with 40k resistance
AIC3204_rset( 57, 0xc0 ); // CM is routed to Right Negative MICPGA via CM1R with 40k resistance
*/
AIC3204_rset( 59, 48 ); // MIC_PGA_L gaine 24dB
AIC3204_rset( 60, 48 ); // MIC_PGA_R gaine 24dB
AIC3204_rset( 0, 0x00 ); // Select page 0
AIC3204_rset( 81, 0xc0 ); // Powerup Left and Right ADC
AIC3204_rset( 82, 0x00 ); // Unmute Left and Right ADC
Wait(100 );
AIC3204_rset( 0, 0x00 ); // Select page 0
AIC3204_rset( 87, 82 ); // Left Noise �����
AIC3204_rset( 95, 82 ); // Right Noise �����
Wait(100 ); // Wait
}
/////////////////////////////////////////////////////////////////////////
// UART functions
/////////////////////////////////////////////////////////////////////////
void UARTinit()
{
//CSL_UartIsrAddr isrAddr;
mySetup.clkInput = GetSysClk();
IRQ_disable(UART_EVENT);
IRQ_clear(UART_EVENT);
UART_init(&uartObj,CSL_UART_INST_0,UART_INTERRUPT);
//SYS_setEBSR(CSL_EBSR_FIELD_PPMODE, CSL_EBSR_PPMODE_1);
hUart = (CSL_UartHandle)(&uartObj);
UART_setup(hUart,&mySetup);
// Configure and Register the UART interrupts
//isrAddr.rbiAddr = uart_rxIsr;
IRQ_plug (UART_EVENT, &UART_intrDispatch);
IRQ_enable(UART_EVENT);
//UART_setCallback(hUart,&isrAddr);
UART_eventEnable(hUart, CSL_UART_RECVOR_LINE_STATUS_INTERRUPT);
UART_eventEnable(hUart, CSL_UART_RECVOR_REG_DATA_INTERRUPT);
flagUART_RX = 0;
}
//--------------------------------------------------------------
tint cmd_count = 0;
interrupt void UART_intrDispatch(void)
{
Uint16 ev = 0;
ev = UART_getEventId(hUart);
if(ev == 2 || ev == 6) // read and timeout
{
while(CSL_FEXT(hUart->uartRegs->LSR,UART_LSR_DR))
{
bufUART[cmd_count] = CSL_FEXT(hUart->uartRegs->RBR,UART_RBR_DATA);
if(cmd_count == 3){
UART_parse();
cmd_count = 0;
}
else
cmd_count++;
}
}
else
cmd_count = 0;
}
//----------------------------------------------------------------------------------
void UART_parse()
{
Uint16 cmd = bufUART[1]*256+bufUART[0];
switch(cmd)
{
case beg_spkr_sel:
SPKR_SEL = bufUART[3]*256+bufUART[2];
cmd_name = cmdSPKR_SEL;
break;
case beg_mic_sel:
MIC_SEL = bufUART[3]*256+bufUART[2];
cmd_name = cmdMIC_SEL;
break;
case beg_mic_short:
MIC_SHORT = bufUART[3]*256+bufUART[2];
cmd_name = cmdMIC_SHORT;
break;
case beg_aer_off_music:
AER_OFF_MUSIC = bufUART[3]*256+bufUART[2];
cmd_name = cmdAER_OFF_MUSIC;
break;
}
flagUART_RX = 1;
}
//----------------------------------------------------------------------------------
void UART_params_apply()
{
switch(cmd_name){
/*case beg_full_pack:
aer_sim_config_aer_params(&siu_inst, &siuSetup);
aer_sim_aep_config(&aepSimInst, &siuSetup.aep_params,
siuSetup.aep_gain_adj_exp, siuSetup.aep_gain_adj_mant);
break;*/
case cmdEMPTY:
break;
case cmdSPKR_SEL:
spkr_sel = SPKR_SEL;
break;
case cmdMIC_SEL:
mic_sel = MIC_SEL;
switch(MIC_SEL){
case 0:
siuSetup.aer_ctl_bitfield_1 = 471;
//siuSetup.aer_ctl_bitfield_1 | aer_CTL1_MUTE_ON;
break;
case 1:
siuSetup.aer_ctl_bitfield_1 = 455;
//siuSetup.aer_ctl_bitfield_1 & (~aer_CTL1_MUTE_ON);
break;
case 2:
siuSetup.aer_ctl_bitfield_1 = 455;
//siuSetup.aer_ctl_bitfield_1 & !aer_CTL1_MUTE_ON;
case 3:
siuSetup.aer_ctl_bitfield_1 = 455;
//siuSetup.aer_ctl_bitfield_1 & !aer_CTL1_MUTE_ON;
break;
}
aer_sim_config_aer_params(&siu_inst, &siuSetup);
aer_sim_aep_config(&aepSimInst, &siuSetup.aep_params,
siuSetup.aep_gain_adj_exp, siuSetup.aep_gain_adj_mant);
break;
case cmdMIC_SHORT:
flagUART_RX = 0;
AIC3204_rset( 0, 0x00 ); // Select page 0
if(MIC_SHORT)
{
AIC3204_rset( 87, 82 ); // Left Noise ����� -30dB
AIC3204_rset( 95, 82 ); // Right Noise ����� -30dB
}
else
{
AIC3204_rset( 87, 0 ); // Left Noise ����� OFF
AIC3204_rset( 95, 0 ); // Right Noise ����� OFF
}
break;
case cmdAER_OFF_MUSIC:
aer_off_music = AER_OFF_MUSIC;
/*AIC3204_rset( 0, 0x00 ); // Select page 0
if(aer_off_music == 1){
AIC3204_rset( 14, 0xC0 );
AIC3204_rset( 11, 0x82 );
}
else{
AIC3204_rset( 14, 0x80 );
AIC3204_rset( 11, 0x84 );
}*/
Wait(200);
break;
}
}
