L1 cache in c6678 multicore dsp

Alex Jivin

Other Parts Discussed in Thread: SYSBIOS

Hello,

I am currently working with the TMDSEVM66788L (The processor is multicore DSP TMS320C6678L) . I have ccs v6 on my pc with mcsdk_2_01_02_05.

I downloaded a project form the TI site that uses lld functions to control EDMA3. I want to know if the L1D and L1P caches are enabled in these examples? If this is not the case how can I enable it?

Thank you in advance,

Alex

over 8 years ago

0 Titusrathinaraj Stalin over 8 years ago

TI__Guru** 116100 points

Please make use of our latest processor SDK package for C6678.
Try to use the following CSL based cache APIs.
CACHE_setL1DSize, CACHE_invL1d, CACHE_invL2, etc.,

C:\ti\pdk_C6678_1_1_2_5\packages\ti\csl\csl_cacheAux.h

0 Raja over 8 years ago

TI__Guru* 81335 points

Hi Alex,

If you are using SYS/BIOS projects, please refer below post from "Uday" for cache configurations.

I think L1P/D should be enabled by default however please check. You can also use EDMA3 APIS to flush and invalidate cache..

Edma3_CacheFlush - Flush the Buffer

Edma3_CacheInvalidate - Invalidate the Buffer

Thank you.

0 Andrey Tereshin over 8 years ago

Prodigy 70 points

Hi Alex,

I don't know what project you are using, but in general there are three places there cashe can be enabled\disabled:
1) GEL script that initializing your hardware before load program
2) In sysbios initialization
3) Manually in your code

Andrey

0 Alex Jivin over 8 years ago in reply to Titusrathinaraj Stalin

Prodigy 170 points

Thank you for your quick response I will try you offer.

0 Alex Jivin over 8 years ago in reply to Raja

Prodigy 170 points

Thank you Raja, I will look it up after I will try Titusrathinaraj's suggestion.

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L1 cache in c6678 multicore dsp