CCS/TMS320C6678: TMS320C6678 1,25 GHz issue

Hi Fabrizio,

Are you certain you've followed the recommendations from the Hardware design Guide for Keystone Devices? Have you followed the power-up sequence presented in TMS320C6678 Datasheet? 

Because you didn't report issues with the initial designs I suspect this is a hardware issue and advise you to revisit your hardware design, especially the powerup sequence. 

Best Regards,
Yordan

hi Yordan,
as I stated in the previous post, the power-up sequence is aderent to the HW design guide for Keystone Devices. in fact, the previous series of this board are all working fine. As i written, the only difference is the DSP frequency (no other modifications occured in the bill of material).
tell me, if i can provide further details to help you to understand my problem.
thanks in advance
Fabrizio

Fabrizio,

Can you put an A part on one of the new boards?

Can you get any CCS connection with this new board?  The error message implies that you have some connectivity.

Can you try to connect to them if they boot into NOBOOT mode?

After reset release, what do you see on the SYSCLKOUT pin?

Tom

hi Tom,

thanks for the fast reply.

for the first step, i'm waiting the component (i think monday).

now, i set the NOBOOT mode in my board and the CCS connection is established; while the GEL file (attached in the post) is executed the following error appears:

I set the PLL value as for the 1,25 GHz (PLL_M = 24, PLL_D=0) as for the 1 GHz (PLL_M = 39, PLL_D = 1) and the result is the same as showed in the picture.

After the reset release, in the SYSCLKOUT pin i see a 16,6 MHz clock.

tell me if I can do other tests.

thanks

Fabrizio1832.evmc6678l.gel

Fabrizio,

I have forwarded this to a CCS expert.

Tom

ok Tom,
i'm waiting for your feedback. it's important to solve the problem.
best regards.
Fabrizio

Fabrizio,

The error from the GEL file occurs when the DSP is trying to access your EMIF configuration registers to configure the DDR timing.
Have you updated any DDR configuration settings in the GEL file? In the GEL file there is a function Global_Default_Setup_Silent which sets up the PLL clocks and configures the DDR : ddr3_setup_auto_lvl_1333

To test this comment out the ddr3_setup_auto_lvl_1333 in Global_Default_Setup_Silent and go to View ->Memory Browser and go to the address indicated in the error 0x21000010 and check if you can read and write to that location. If you have an EVM check the behavior on the EVM and compare it to that on your custom board. does the DDR part you have support 1333 speeds and if yes then did you change the EMIF configuration to match your DDR.?

Alternately, commenting the function, will skip initializing DDR and you may be able to run code from MSMC to test your DDR setup.

Regards,
Rahul

hi Rahul,

as you can see from the GEL file attached in the previous post, the DDR frequency is set to 1066. i commented the ddr3_setup_auto_lvl_1333 and the error is changed:

then, i can't read the memory because the DSP is hang.

the same test executes succesfully on the first generation board (the one with 1 GHz DSP).

do you have any other suggestions?

best regards

Fabrizio

Fabrizio,

You have established that you can connect and run a GEL file.  Did you go through the process to properly design and then commission the DDR3 interface?  This will result in customization to the GEL file and user software.

DDR3 commissioning is in 2 parts: proper board design and proper software configuration.  The DDR3 Layout Guidelines must be followed to obtain a properly routed board.  Then the steps in the DDR3 Initialization Guide must be followed to get the DDR3 Controller and PHY properly configured to communicate robustly with the DDR3 SDRAM.

Please review the initialization sequence documented in the KeyStone I DDR3 Initialization Application Report (SPRABL2E) at: http://www.ti.com/lit/an/sprabl2e/sprabl2e.pdf. There are 2 spreadsheets (PHY_CALC & REG_CALC) that can be downloaded with this document that assist with register configuration.  Additional detail is in the KeyStone DDR Layout Guidelines and the KeyStone I DDR User Guide.  All are available from the C6678 web page at: www.ti.com/.../TMS320C6678.

To fill out the PHY_CALC spreadsheet, you will need a report showing that the length matching rules have been met.  An example is attached below.  Please attach a similar report along with the populated spreadsheets for review.

Tom

0456.EVM_DDR3_Rules.xls

Tom,

as i posted in the past, my design isn't new, but i had many boards without any problem. the only difference in these boards is the DSP C6678 (1,25 Ghz instead of 1 GHz).

however, in the attachment you find the form compiled with the values of our board (extract from the PCB tool).

0268.0456.EVM_DDR3_Rules_Gualtieri.xls

i want add a little information more; i comment out the ddr3_memory_test in GEL file and a new error appears:

can this be useful? have you some other suggestion about?

best regards

Fabrizio

Fabrizio,

The length matching report shows that the routing for the data group nets is proper.  However, the report does not show that the fly-by routing for the ADD/CMD/CTRL/CLK has been properly implemented.  This is critical for robust operation.  The report needs to show the routed length from the controller to each of the DDR3 SDRAMs.  Please update the report with this information.  If you cannot directly extract this for the CAD tool, this can be populated manually.  This information is also needed to populate the PHY_CALC spreadsheet which produces values needed by the software.

Tom

Tom,
i don't know if i can extract these informations. Why are you insisting on DDR3 memories? as i mentioned in the first post, when the DSP is in SPI boot, the DSP don't link with CCS. In this case, what is the impact of the memories?
best regards
Fabrizio

Fabrizio,

I thought that you previously observed that the GEL execution was hanging on the DDR3.  That is why I am trying to help you get through the DDR3 commissioning process.

If you are only concerned with the problem of connecting CCS when in SPI boot, you are probably encountering a software error.  It is not unusual for cores to get into a state where you cannot connect CCS after a hang.  In that case, you have to reset the core and that causes you to lose the debug state information.  Rahul should be able to help with that debug.

Tom

Tom,
I would like to understand both of these things. in particular I would like to know why a board that worked properly, now it doesn't work DSP side, having only changed the DSP (1,25 GHz instead of 1 GHz).
best regards

Fabrizio,

Therefore, I see 3 paths for progress:

1.  Follow the steps for DDR3 interface commissioning.  The length matching rules must be met, especially for the fly-by nets.  The results from this exercise are needed in the PHY_CALC spreadsheet.  Once you have a completed length matching report and completed PHY_CALC and REG_CALC worksheets, we can review them for you.

2.  Replace a 1.25GHz DSP with a 1.00GHz DSP to validate the assumption that changing the DSP speed grade is the only significant change.

3.  Also, if there is more that you want to do with the GEL file from NOBOOT, please let us know what additional tests that you want to run where you are not using DDR.  You should be able to load test programs to validate all of the board circuitry.  You should also measure the SYSCLKOUT to make sure the MAIN PLL is running at the expected rate.

Tom