ECC issue with DM36x processor

Chris Hassapis

Other Parts Discussed in Thread: TMS320DM365

Advisory 1.2.4 of the errata document for TMS320DM365 Silicon Revision 1.1 and 1.2 describes an ECC issue that seems to be related to the condition where more than 4 errors are found. The advisory describes the code changes that address this issue which have been incorporated into the latest release.

One of the e2e forum posts (see links below) describes an ECC issue which seems to be timing related (i..e. the ECC has not finished its calculations before other process are initiated.) Code modifications which supposedly address this issue are given at the end of the thread.

http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/100/p/266652/935165

http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/100/p/182730/708236.aspx#708236

Question 1. Are these two different issues that require two different code changes? Or are they both addressed by the code changes described in Advisory 1.2.4 of the errata?

Question 2. If they are different issues, has the timing-related ECC issue been addressed in the latest release?

Thanks,

Chris

over 7 years ago

0 Cesar over 7 years ago

TI__Guru*** 138439 points

Hi Chris,

I think there is some confusion. The issues in the threads you mentioned were caused by the use of an old UBL which did not include the Advisory 1.2.4 fix.

In order to be productive let's do the following

1) Please check your UBL code and let us know if you have the Advisory 1.2.4 fix implemented.
2) If the Advisory 1.2.4 fix is not implemented in your UBL, please implement it, rebuilt the UBL and check if the issue is fixed.

thanks!
Cesar

0 Michael Scherban over 7 years ago in reply to Cesar

TI__Genius 12320 points

Hi Chris,

The mentioned advisory and the forum threads are two separate issues that require two separate code fixes. They are both fixed in the latest releases.

The advisory issue has to do when 5 bit errors are found which causes the logic to not read certain registers.

The issue from the linked e2e threads are due to a race condition that occurs when the ECC is started and the code thinks it has completed, when it has not yet begun.

Regards,
Mike

0 Chris Hassapis over 7 years ago in reply to Michael Scherban

Prodigy 30 points

Michael, many thanks for your reply, this precisely answers our two questions. Are there any release notes. errata, or an advisory that documents that the timing related ECC issue has been addressed in the latest FW release?

0 Michael Scherban over 7 years ago in reply to Chris Hassapis

TI__Genius 12320 points

Hi Chris,

This link here to the release notes should be visible to you: processors.wiki.ti.com/.../DaVinci_PSP_03.21.00.04_Release_Notes

This refers to SDOCM00075224 which is the ticket for the issue, but the contents of it won't be visible to you.

It points to this patch where this was fixed: arago-project.org/.../

However on the release branch, this is the patch: arago-project.org/.../

Regards,

Mike

0 Chris Hassapis over 7 years ago in reply to Michael Scherban

Prodigy 30 points

Mike, got it, many thanks.

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ECC issue with DM36x processor