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OMAP-L137: OMAP-L137 Crystal Selection

EE_MT
Intellectual 390 points
Part Number: OMAP-L137

The datasheet for the OMAP-L137 (page 61) states that for input clock frequencies between 20 and 30 MHz, a crystal with 60 ohm max ESR is recommended and typical load capacitance values are 10-20 pF. I have been searching for a crystal with a 4-SMD (2.5mm x 2.00mm) package to replace the original crystal that is now obsolete in my design. This is the crystal that I found that comes closest to meeting the OMAP-L137 requirements: 

MFG PN: NX2520SA-24.576000MHZ

MFG: NDK America, Inc.

It has a Load Capacitance of 10 pF (Requirement is 10-20pF)

However, it has an ESR of 70 ohm (Requirement per the datasheet is 60 Ohm max). Will this be a problem?

Thanks

  • 0
    TI__Guru 65405 points
    I've forwarded this to the HW design experts. Their feedback should be posted here.

    BR
    Tsvetolin Shulev
  • 0
    TI__Guru**** 161600 points
    Hi,

    However, it has an ESR of 70 ohm (Requirement per the datasheet is 60 Ohm max). Will this be a problem?

    Crystals can be modeled by a series circuit of an inductor, a capacitor, and a resistor along with a shunt capacitor in parallel with all three. The value of the resistor is known as the equivalent series resistance (ESR) and it relates to bulk losses inside the quartz crystal. The ESR quantifies the loading of the crystal and the resonance circuit seen at the oscillator pins of the device.
    ESR values become important when resistance values reach a point were the oscillator circuit cannot adequately drive the crystal. This may result in sluggish start-up or operation of the crystal at an unwanted mode.

    So yes, this could cause issues with your device in some use cases. I'd recommend to follow the datasheet recommendations and find a crystal that meets the requirements.

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    Intellectual 390 points

    I'm assuming the same is true for the load capacitance?

    For the OMAP-L137, the clock signals have to route through vias do to the pins being F2 (OSCIN), F1 (OSCOUT) and E2 (OSCVSS). With that being said, when choosing the series capacitor values for the crystal, do you typically add approximately 3 - 5 pF to the value to account for the parasitic capacitance?

    Example: Cload = ( (C1+Cparasitic) * (C2+Cparasitic) ) / ( (C1+Cparasitic) + (C2+Cparasitic) )

  • 0 in reply to EE_MT
    TI__Guru**** 161600 points
    Hi,

    Correct, the load capacitance must meet the datasheet requirements. For further guidance you can check the following wiki:
    processors.wiki.ti.com/.../_AM1x_Schematic_Review_Checklist

    Best Regards,
    Yordan