Linux/PROCESSOR-SDK-AM335X: Disable IO reset at boottime

STFZ

Tool/software: Linux

Hi,

I have set a GPIO pin to "high" in the u-boot board file by function "gpio_set_value(gpio, val)"
This works properly until kernel message "Initializing cgroup subsys io" during kernel startup is reached.
After that the GPIO pin is "low".

How can I avoid IO reset?

BR
Stefan

over 7 years ago

0 Yordan Kovachev over 7 years ago

TI__Guru**** 161600 points

Hi Stefan,

See this thread:
e2e.ti.com/.../2147766

With u-boot & dts configurations shown there, I was able to get the GPIO maintain its state throughout the entire boot process (from MLO to linux command line).

Best Regards,
Yordan

0 STFZ over 7 years ago in reply to Yordan Kovachev

Intellectual 600 points

Hi Yordan,

Thank you for this workaround by enabling pull-up resistors. Is it possible to get the GPIO maintain its state (set by "gpio_set_value") throughout the entire boot process?

BR
Stefan

0 Yordan Kovachev over 7 years ago in reply to STFZ

TI__Guru**** 161600 points

Hi Stefan,

No, I think the gpio state will reset every time u-boot passes control to linux kernel, because kernel driver re-configures the gpio controller (i need to dig a little more in the sources).
By configuring the pinmux (internal pullup resistor) you get a steady I/O cell state.

Best Regards,
Yordan

0 STFZ over 7 years ago in reply to Yordan Kovachev

Intellectual 600 points

Hi Yordan,

I'm facing the same problem at PWM generation (ePWM-Module). But sometimes the PWM output will not reset.

G, Stefan

0 Yordan Kovachev over 7 years ago in reply to STFZ

TI__Guru**** 161600 points

Hi,

But sometimes the PWM output will not reset

So you need the pwm pins to reset between u-boot & linux kernel, right?
Which pins do you use for pwm?

Best Regards,
Yordan

0 STFZ over 7 years ago in reply to Yordan Kovachev

Intellectual 600 points

Hi Yordan,
The pwm pins should not be resetted.
Pins: gpmc_a2 (ehrpwm1a), spi0_sclk (ehrpwm0a), spi0_d0 (ehrpwm0b), gpmc_a3 (ehrpwm1b)

0 STFZ over 7 years ago in reply to STFZ

Intellectual 600 points

Hi Yordan,

Do you have any suggestions how to solve the problem?

BR
Stefan

0 Yordan Kovachev over 7 years ago in reply to STFZ

TI__Guru**** 161600 points

Hi Stefan,

I didn't get the time to test this... sorry.

Did you try with configuring the pins in u-boot, as well as linuc kernel?

Best Regards,
Yordan

0 STFZ over 7 years ago in reply to Yordan Kovachev

Intellectual 600 points

Hi Yordan,

Yes, I did.

The registers pwmss_ctrl of CONTROL_MODULE, CM_PER_EPWMSS0_CLKCTRL and CM_PER_EPWMSS1_CLKCTRL are resetted to default during kernel startup:
pwmss_ctrl (0x44E1_0664): 0x00000000
CM_PER_EPWMSS0_CLKCTRL (0x44E0_00D4): 0x00030000
CM_PER_EPWMSS1_CLKCTRL (0x44E0_00CC): 0x00030000

The registers of PWM Subsystem 0 and 1 are NOT changed.

BR
Stefan

0 STFZ over 7 years ago in reply to STFZ

Intellectual 600 points

nm_nico is also faced with the same problem: e2e.ti.com/.../2040522

Until now there has been no solution

0 STFZ over 7 years ago in reply to STFZ

Intellectual 600 points

I think something has to be changed in directory .../board-support/linux-4.4.32.../arch/arm/mach-omap2
Please see e2e.ti.com/.../202539

0 Yordan Kovachev over 7 years ago in reply to STFZ

TI__Guru**** 161600 points

Hi,

Can you share your dts nodes? I mean ehrpwm pinmux settings & the &pwm node.

Best Regards,
Yordan

0 STFZ over 7 years ago in reply to Yordan Kovachev

Intellectual 600 points

Hi Yordan,

The relevant parts of dts-file:

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/am33xx.h>
#include "skeleton.dtsi"

/ {
...
ocp: ocp {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
ti,hwmods = "l3_main";
...
epwmss0: epwmss@48300000 {
compatible = "ti,am33xx-pwmss";
reg = <0x48300000 0x10>;
ti,hwmods = "epwmss0";
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
ranges = <0x48300100 0x48300100 0x80 /* ECAP */
0x48300180 0x48300180 0x80 /* EQEP */
0x48300200 0x48300200 0x80>; /* EHRPWM */

ecap0: ecap@48300100 {
compatible = "ti,am3352-ecap",
"ti,am33xx-ecap";
#pwm-cells = <3>;
reg = <0x48300100 0x80>;
clocks = <&l4ls_gclk>;
clock-names = "fck";
interrupts = <31>;
interrupt-names = "ecap0";
status = "disabled";
};

ehrpwm0: pwm@48300200 {
compatible = "ti,am3352-ehrpwm",
"ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x48300200 0x80>;
clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
clock-names = "tbclk", "fck";
status = "disabled";
};
};

epwmss1: epwmss@48302000 {
compatible = "ti,am33xx-pwmss";
reg = <0x48302000 0x10>;
ti,hwmods = "epwmss1";
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
ranges = <0x48302100 0x48302100 0x80 /* ECAP */
0x48302180 0x48302180 0x80 /* EQEP */
0x48302200 0x48302200 0x80>; /* EHRPWM */

ecap1: ecap@48302100 {
compatible = "ti,am3352-ecap",
"ti,am33xx-ecap";
#pwm-cells = <3>;
reg = <0x48302100 0x80>;
clocks = <&l4ls_gclk>;
clock-names = "fck";
interrupts = <47>;
interrupt-names = "ecap1";
status = "disabled";
};

ehrpwm1: pwm@48302200 {
compatible = "ti,am3352-ehrpwm",
"ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x48302200 0x80>;
clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>;
clock-names = "tbclk", "fck";
status = "disabled";
};
};
};
...
&am33xx_pinmux {
pinctrl-names = "default";
pinctrl-0 = <&clkout2_pin>;
...
ehrpwm0_pins: ehrpwm0_pins {
pinctrl-single,pins = <
0x150 (PIN_OUTPUT | MUX_MODE3) /* P9_22, A17 */
0x154 (PIN_OUTPUT | MUX_MODE3) /* P9_21, B17 */
>;
};
ehrpwm0_pins_sleep: ehrpwm0_pins_sleep {
pinctrl-single,pins = <
0x150 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* P9_22, A17 */
0x154 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* P9_21, B17 */
>;
};

ehrpwm1_pins: ehrpwm1_pins {
pinctrl-single,pins = <
0x48 (PIN_OUTPUT | MUX_MODE6) /* P9_14, U14 */
0x4C (PIN_OUTPUT | MUX_MODE6) /* P9_16, T14 */
>;
};
ehrpwm1_pins_sleep: ehrpwm1_pins_sleep {
pinctrl-single,pins = <
0x48 (PIN_INPUT_PULLDOWN | MUX_MODE6) /* P9_14, U14 */
0x4C (PIN_INPUT_PULLDOWN | MUX_MODE6) /* P9_16, T14 */
>;
};
...
};
...
&epwmss0 {
status = "okay";

ehrpwm0: pwm@48300200 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ehrpwm0_pins>;
pinctrl-1 = <&ehrpwm0_pins_sleep>;
};
};

&epwmss1 {
status = "okay";

ehrpwm1: pwm@48302200 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ehrpwm1_pins>;
pinctrl-1 = <&ehrpwm1_pins_sleep>;
};
};
...
&ocp {
pwmdriver@0 {
compatible = "pwm-driver";
...
status = "okay";

epwm0 {
pwms = <&ehrpwm0 0 25000 0>; // pwm period in ns
};
epwm1 {
pwms = <&ehrpwm1 0 25000 0>; // pwm period in ns
};
};
};

0 Jason Reeder over 7 years ago in reply to STFZ

TI__Genius 10415 points

Hi,

Can you try adding the following line to both the am33xx_epwmss0_hwmod and the am33xx_epwmss1_hwmod structures in the arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c file:
.flags = HWMOD_INIT_NO_RESET,

Similar to the commit that one of your other reference posts referenced (http://arago-project.org/git/projects/?p=linux-am33x.git;a=commit;h=0c2a044c5368a0ba37d103bb56cc841cc12fb63a).

Jason Reeder

0 Yordan Kovachev over 7 years ago in reply to Jason Reeder

TI__Guru**** 161600 points

Hi,

Regarding I/O reset of EHRPWM1 pins. I tested this with your configurations on my BBB, probed P9_14 (EHRPWM1A). Here are my modifications:
1. U-boot modifications:
-In board/ti/am335x/mux.c:
static struct module_pin_mux uart5_pin_mux[] = {
{OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */
{OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */
{-1},
};

+ static struct module_pin_mux gpio0_20_pin_mux[] = {
+ {OFFSET(xdma_event_intr1), (MODE(7) | PULLUDEN)}, //works well with PULLUP_EN, test with PULLUDEN
+ {-1},
+ };

+ static struct module_pin_mux ehrpwm1_pin_mux[] = {
+ {OFFSET(gpmc_a2), (MODE(6) | PULLDOWN_EN)},
+ {-1},
+ };
===========
configure_module_pin_mux(uart3_pin_mux);
}

+ void enable_ehrpwm1_pin_mux(void)
+ {
+ configure_module_pin_mux(ehrpwm1_pin_mux);
+ }

+ void enable_gpio0_20_pin_mux(void)
+ {
+ configure_module_pin_mux(gpio0_20_pin_mux);
+ }

=========
configure_module_pin_mux(mmc0_pin_mux);
+ configure_module_pin_mux(gpio0_20_pin_mux);
+ configure_module_pin_mux(ehrpwm1_pin_mux);

-In board/ti/am335x/board.c:
void set_uart_mux_conf(void)
{
+ enable_gpio0_20_pin_mux();
+ enable_ehrpwm1_pin_mux();

2. Linux kernel modifications:
- In arch/arm/boot/dts/am335x-bone-common.dtsi:
&am33xx_pinmux {
pinctrl-names = "default";
+ pinctrl-0 = <&gpio0_pins>;

===========
+ gpio0_pins: gpio0_pins {
+ pinctrl-single,pins = <
+ 0x1b4 (PIN_OUTPUT_PULLUP | MUX_MODE7)
+ >;
+ };

+ ehrpwm1_pins: ehrpwm1_pins {
+ pinctrl-single,pins = <
+ 0x48 (PIN_OUTPUT | MUX_MODE6) /* P9_14, U14 */
+ 0x4C (PIN_OUTPUT | MUX_MODE6) /* P9_16, T14 */
+ >;
+ };

=========
+ &epwmss1 {
+ status = "okay";

+ ehrpwm1: pwm@48302200 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&ehrpwm1_pins>;
+ };
+ };

As I said, I probed P9_14 (EHRPWM1A) with a scope, and the pin was constantly low through the entire boot process (u-boot & linux kernel). To be sure the settings have taken effect I checked the register values at both stages:
u-boot:
=> md 0x44E10848
44e10848: 00000006 //==> conf_gpmc_a2 set to MUXMODE6, PULLUPDOWN disabled.

kernel:
root@am335x-evm:~# devmem2 0x44E10848
/dev/mem opened.
Memory mapped at address 0xb6f37000.
Read at address 0x44E10848 (0xb6f37848): 0x0000000E //===> conf_gpmc_a2 set to MUXMODE6, PULLUPDOWN enabled
// PULLDOWN selected

I will check with .flags = HWMOD_INIT_NO_RESET, as Jason suggested, to verify that the registers are NOT reset as well.

Best Regards,
Yordan

0 STFZ over 7 years ago in reply to Jason Reeder

Intellectual 600 points

Hi Jason,

I have already added this line. It doesn't help.
I will double check this...

Thanks,
Stefan

0 Yordan Kovachev over 7 years ago in reply to STFZ

TI__Guru**** 161600 points

Hi Stefan,

The registers you monitor:
pwmss_ctrl (0x44E1_0664): 0x00000000
CM_PER_EPWMSS0_CLKCTRL (0x44E0_00D4): 0x00030000
CM_PER_EPWMSS1_CLKCTRL (0x44E0_00CC): 0x00030000
are not pwmss registers. The first one PWMSS_CTRL belongs to the Control Module, and the following two registers CM_PER_EPWMSS0_CLKCTRL & CM_PER_EPWMSS1_CLKCTRL are part of the PRCM, so I think this is the reason, why having .flags = HWMOD_INIT_NO_RESET in the PWMSS structures of omap_hwmod_33xx_43xx_ipblock_data.c does not affect the above mentioned registers.

From my experience, the PRCM registers are set to MODULEMODE = 0x2 (ENABLE : Module is explicitly enabled) => 0x00030002, ONLY when you start the pwmss from sysfs. If you don't output pwm pulses on EHRPWM1A/EHRPWM1B pins the module will stay disabled.

EDIT: The CTRL_MODULE register, pwmss_ctrl (0x44E1_0664) should retain its state, if it is set in u-boot. Do you configure PWMSS_CTRL register anywhere in your u-boot?

Best Regards,
Yordan

0 Jason Reeder over 7 years ago in reply to Yordan Kovachev

TI__Genius 10415 points

Stefan,

One more thing to try. Can you add the following two attributes to your epwmss0 and epwmss1 device tree nodes:

ti,no-idle-on-init;

ti,no-reset-on-init;

E.g.

epwmss0: epwmss@48300000 {

...

ti,hwmods = "epwmss0";

ti,no-idle-on-init;

ti,no-reset-on-init;

...

status = "disabled";

...

}

After talking to one of our kernel developers, you should be able to undo your modification to the omap_hwmod_33xx_43xx_ipblock_data.c file and use these attributes to achieve the same goal.

Just to be sure we are on the same page, you are configuring the PWMSS peripherals during u-boot to generate a PWM signal and as the kernel starts you see the PWM signals stop working, correct? Which appears to be due to the kernel disabling the clocks to the peripheral?

Jason Reeder

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Linux/PROCESSOR-SDK-AM335X: Disable IO reset at boottime