I'm migrating a design from a Pericom PI7C8152B to the PCI2060I bridge for an industrial temperature application. My system uses the bridge so that the secondary side, which runs from a 33-MHz fixed-frequency oscillator, does not slow down the system when plugged into a 66 MHz primary side bus. The Pericom chip had a somewhat different clocking scheme and I want to be sure I get it right when I do the re-spin.
In the Pericom part, I needed to use a clock distribution buffer to run the clock from my oscillator to each secondary load and the bridge's S_CLK input pin. It did not have a separate SEC_ASYNC_CLK input like the PCI2060I. If I understand it correctly, the PCI2060I should be able to take the oscillator signal (3.3V CMOS) and then all I need to do is configure SEC_ASYNC_RATE high, S_ASYNC_SEL high, and I can use the secondary clocks in the typical fashion of a synchronous bridge, i.e. S_CLKOUT9 looped to S_CLK and other S_CLKOUTx pins to secondary loads.
Is this correct? Are there any other gotcha's that might prevent the use of this bridge with a fixed 33 MHz secondary clock? And in this mode, does it matter what I do with the S_M66ENA pin?
