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TLK10232 with 10G SFP+ optical tranceiver

Other Parts Discussed in Thread: TLK10232

Hi.

I'm confused what mode should I set for my application.

FPGA(XAUI) <-> TLK10232 <-> SFP+(optic)

I configured according to set from forum

TLK10232 10G-KR Setting 

But have no link to switch with shallow loopback

write 1 to 1E bit 0

Thanks,

Yuli

  • Hi Yuli,

    For XAUI to SFI/XFI operation, you will need to configure the device for 10GBASE-KR mode and disable the features specific to backplane Ethernet like Clause 73 Auto-Negotiation and 10G Link Training. To do this, follow this procedure:

    1. Reset device (write a 1 to 0x1E.0000 bit 15 or assert RESET_N pin)

    2. Make sure the reference clock selection (156.25 MHz or 312.5 MHz) is correct – this is done through register 0x1E.001D bit 12 (default is 156.25 MHz).

    3. Disable auto-negotiation by writing 1’b0 to 0x07.0000 bit 12

    4. Disable link training by writing 16’h0000 to 0x01.0096. 

    5. Enable Deep Local Loopback by writing 16’h0D12 (Enable bit 2).

    6. Write 16’h03FF to 0x1E.8020.  This allows the link settings that would normally be configured through KR training to be configured manually instead.

    7. Depending on the link conditions, you may need to change the default configuration of 0x1E.0003 and 0x1E.0004.  For optical connections, we typically recommend changing HS_ENTRACK (0x1E.0004 bit 15) to 1’b1 and HS_EQPRE (0x1E.0004 bits 14:12) to 3’b101.  This can be a starting point, but you may need to do some BER testing to optimize the values (tuning process).

    8. Issue a data path reset by writing 1’b1 to 0x1E.000E bit 3. This is needed always that desired settings are applied.

    ***At this point the device should be properly configured.

    I hope this helps.

    Best Regards,

     

    Luis Omar Morán Serna

    High Speed Interface

    SWAT Team

  • Hi, Luis.

    Please, specify register in p.5

    Regards,
    Yuli
  • Hello Yuli,

    Sorry for the confusion, if you are going to use Shallow Loopback mode, this is the procedure:

    1. Reset device (write a 1 to 0x1E.0000 bit 15 or assert RESET_N pin)

    2. Make sure the reference clock selection (156.25 MHz or 312.5 MHz) is correct – this is done through register 0x1E.001D bit 12 (default is 156.25 MHz).

    3. Disable auto-negotiation by writing 1’b0 to 0x07.0000 bit 12

    4. Disable link training by writing 16’h0000 to 0x01.0096.

    *5. Enable Shallow Local Loopback by writing 16’h0D11 (Enable Bit 0).

    6. Write 16’h03FF to 0x1E.8020.  This allows the link settings that would normally be configured through KR training to be configured manually instead.

    7. Depending on the link conditions, you may need to change the default configuration of 0x1E.0003 and 0x1E.0004.  For optical connections, we typically recommend changing HS_ENTRACK (0x1E.0004 bit 15) to 1’b1 and HS_EQPRE (0x1E.0004 bits 14:12) to 3’b101.  This can be a starting point, but you may need to do some BER testing to optimize the values (tuning process).

    8. Issue a data path reset by writing 1’b1 to 0x1E.000E bit 3. This is needed always that desired settings are applied.

    ***At this point the device should be properly configured.

    Best Regards,

    Luis Omar Morán Serna

    High Speed Interface

    SWAT Team

  • Thanks a lot, Luis.
    It is working.

    I just have some BER on one lane of XAUI according to register 1e.11
    Is it possible to trim setting? Sensitivity or something?

    Yuli

  • Hi Yuli,

    Please refer to 0x1E.0007 and 0x1E.0008. Basically these 2 registers control the rx and tx settings for low speed side of the device.

    Best Regards,
    Luis Omar Morán Serna
    High Speed Interface
    SWAT Team
  • Hi, Luis.

    Unfortunately I cannot write to those regs.
    Any attempt to write return "0"
    Any others are writable.

    Yuli