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TLK100 incorrect MII clock speed

Ben Stelle
Intellectual 620 points
Other Parts Discussed in Thread: TLK100

Hello, I have run into a problem with the TLK100 Ethernet chip.  We have been using this chip for some time now with no problems at all until we tried to use the chip on a new board.  Now we are seeing things that I cannot explain based upon the data sheet and even comparison between our working product and the new one.  Specifically, the MII TX CLK and the MII RX CLK are mysteriously running at 5.0 Mhz instead of the 2.5Mhz that we have been used to seeing on the working product.  The datasheet only says either 25Mhz or 2.5Mhz should be expressed by the TLK100 on these chips.  There is no mention I can find of 5Mhz.  I don't know if this means we are inexplicably in some sort of product test mode, or we have bad chips.  The chips have the TLK100 part number on them, the TI logo, and the following 2 lines of text 3AT, and C4X4.  One of our legacy products has the same part number and logo, but has 09T, D18K.  I don't know if this tells me anything or not.  Other symptoms of malfunction that I have on this board are the lack of link and activity indicators as occur on the working targets.  I have checked that the 25Mhz oscillator is running, and the waveforms look the same on the scope as the working boards to include the 25Mhz output.  Is there some way to put the chip in this odd state that can be corrected, or detected under code control?

  • 0
    TI__Mastermind 21346 points

    Hi Ben,

    I am going to move your question to the Ethernet forum so that it can get the proper support and visibility. They should be able to address you question.

    Thanks!

     

    John

  • 0 in reply to John Griffith
    TI__Intellectual 2000 points

    Hi Ben,

    regarding the Rx and Tx clocks you are correct. they should be either 2.5 or 25Mhz.  i suggest you attach the schematic of your board so we could review it. 

    Thanks,

    Aviad

  • 0 in reply to aviad
    Intellectual 620 points

    3326.S2072360000_-.pdf

    I don't know if the PDF file I tried to attach above worked or not.  Let me know and I can resend it.  I also snipped a PNG (above) just in case.

    Even though it isn't supposed to make 5Mhz signals there, is there any way that the hardware is capable of doing it?

    Again, we have used this chip on hundreds of legacy boards with no problems at all up to now.  So, this is most unexpected for us.

    Any insight will help.

    Thanks,

    Ben

  • 0 in reply to Ben Stelle
    TI__Intellectual 2000 points

    Hi Ben,

    1. I have observed the schematic, thanks.
    2. on how many boards have you seen this behavior?
    3. did you try to replace the PHY? if yes than did you try replacing the PHY with the chips that are working and have been labeled " 09T, D18K"

    could you also double check the following:

    1. scope the signalling on the transmit pair (the TD+ and TD-) on the RJ45, or after the magnetic. if you can do it with differential probe it will be good. when there is no link. there still should be NLP (normal link pulse) signal
    2. scope the 25Mhz Xi pin
    3. scope the CLK25OUT. 
    4. you mention that the led  indications behave different from working board, what do you observe? what is the difference between working and non working board. when there is no link?
    5. could you take scope measurements of the:
      1. VDD33V18
      2. V18PFBOUT
      3. VDD33VD11
    6. how is the RESETN pin handled ? according to DS: "At power up it is recommended to have the external reset pin (RESETN) active (low). The RESETN pin should be de-asserted 200us after the power is ramped up to allow the internal circuits to settle and for the internal regulators to be stabilized."
    7. do you have register access? if yes, than please send register readings from address space 0x0 to 0x1f(h)

    Thanks,

    Aviad

  • 0 in reply to aviad
    Intellectual 620 points

    Aviad, we are having problems on all 5 of our prototypes of the new boards.  I have not tried replacing the PHY on any of these boards yet but will be trying that next.

    I did scope the TD+ and TD- on our good boards and found that there were NLP signals of opposite polarities from each other as expected.  However, on the problem boards there are no link pulses of any kind without an active Ethernet connection.

    The 25Mhz crystal connections all look good and identical to the old working board.

    The 25Mhz clock output looks good on all of them as well, and identical with old working board.

    For most of the targets I see no LEDs even on first power up, only one shows a brief flash on cold start, but no lights from any on active Ethernet connection unlike working board where both LEDs are active as expected.

    On all of the boards all of the supply rails all look stable and at the correct voltage to include the 1.8 and 1.1 rails.

    It takes our boards a while to start up, so the sequence for release of reset is as follows:

    1.  VDD comes up.

    2.  RESET and ENABLE remain undefined for 334ms after power is asserted.

    3.  RESET and ENABLE are finally taken low and held until 790ms after power was first asserted.

    4.  ENABLE is brought to logic high (VDD).

    5.  33ms after the ENABLE is brought high, RESET is brought to logic high(VDD).  The 25Mhz clock oscillator has been running for some time before this, so when RESET is released the 25Mhz clock output begins immediately.

    6.  25ms after RESET is released the TX and RX clock outputs begin to come to life and appear to start at a very low frequency (~130Khz) and increase in speed until reaching the final achievable speed.

    Of our 5 targets the following are the symptoms:

    1.  RX and TX clocks are stable at 5Mhz, voltage rails and 25Mhz osc and output are all stable, no link pulses

    4.  same symptoms as 1 above.

    2.  RX and TX clocks are unstable (excessive jitter) at ~1.37Mhz, voltage rails and 25Mhz osc and output are all stable, no link pulses.

    3.  same symptoms as 2 above.

    5.  RX and TX clocks are unstable (excessive jitter) at ~3Mhz, voltage rails and 25Mhz osc and output are all stable, no link pulses. 

    We did attempt to access the registers on one of these units and were unable to get reasonable or even consistent results from attempt to attempt.

  • 0 in reply to Ben Stelle
    Intellectual 620 points

    Aviad, I have located the problem finally.  We replaced a couple of chips with no improvement.  However, in probing with my finger around the bypass capacitors for pins 2,4, and 40, I found that the RX and TX clocks were very sensitive to my touch suggesting some sort of grounding issue.  In checking the board layout, the routing for capacitors C3, and C5 were fine (both 0.1uF), but the ground connection for C1 (1.0uF) was indirect and ran for nearly 1/2" before connecting to ground.  I then tried probing with a small capacitor to ground (my scope probe) and found anywhere along that ground trace that the capacitance basically fixed the issue.  Anyway, the final fix was to scrape the trace and some adjacent ground plane and directly bridge the two  together making for a much better ground connection on that capacitor.  Now, everything is as stable as it was on the original board.  So the moral of the story is to make sure all of the bypass capacitors have a very direct connection to ground on this chips layout.

    Thanks for your help in this matter.

    Ben

  • 0 in reply to Ben Stelle
    TI__Intellectual 2000 points

    Ben,

    you are welcome. Thanks for sharing this debug effort and board routing issue.

    Aviad