DS90UH940-Q1: input signal spec (RINx pin)

Nao

Genius 4905 points

Part Number: DS90UH940-Q1

Hi, E2E members,

I can find following spec in DS90Ux92x series datasheet.
But, I can't it in DS90Ux94x series datasheet.

Could you tell us input signal spec (RINx pin) for DS90UH940?

Regards,

Nao

over 5 years ago

0 Jonathan Nguyen over 5 years ago

TI__Expert 4555 points

Nao,

The Deserializer PLL Lock time is 5ms (typ) and 10ms (max), where PLL lock time is measured from the time PDB goes HIGH until the LVDS outputs are active, with a valid clock input to RIN. These specs are for the condition 25 MHz < PCLK < 165 MHz.

The input jitter spec is 0.3 UI (Max).

Regards,
Jonny

0 Nao over 5 years ago in reply to Jonathan Nguyen

Genius 4905 points

Hi, Jonathan

Thank you for you feedback.
Do you have a plan to add this spec in the datasheet?

Regards,
Nao

0 Jonathan Nguyen over 5 years ago in reply to Nao

TI__Expert 4555 points

There are no plans currently, but I can pass the issue along to see if it can be included.

Best Regards,
Jonny

0 Nao over 5 years ago in reply to Jonathan Nguyen

Genius 4905 points

Hi, Jonny

We will check Input and Output jitter in customer board first,
if there is link issue at Failure Analysis. so, we need this spec in datasheet.

Regards,
Nao

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DS90UH940-Q1: input signal spec (RINx pin)