DS125DF1610 Raw Mode

Hi Greg,

The data path to the output driver in the DS125DF1610 goes through the FIR block. The FIR block is a digital equalization circuit that requires clock information from the CDR in order to operate normally. If the CDR is bypassed, no clocks are generated for the FIR.

In order to transmit data out of a channel while the CDR is bypassed, you will need to reprogram the FIR. For this use case, configure the main cursor and post cursor taps to a weight of 0. Then program the pre cursor tap to your desired amplitude.

You can find the registers for the pre cursor, main cursor and post cursor in channel registers 0x3D, 0x3E and 0x3F. Be sure to only set the tap weights and desired polarities in these registers. In these registers bit 7 can have other functionality.


Mike Wolfe
DPS APPS / SVA

Hi Mike,

Thanks for your reply. I set the pre, main, and post cursors as you suggested above. Here is a register dump that shows signal detect and CDR lock. Data is output.

     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f
00: 00 80 dc 00 01 01 01 01 60 20 50 6f 08 b4 93 69
10: 3a 20 e0 90 00 13 7a 36 40 20 a0 03 90 00 00 55
20: 00 00 00 40 00 01 bd 37 b4 60 30 0f f2 01 00 f6
30: 00 58 11 88 bf 1f 30 00 10 00 00 3e 33 00 2c 80
40: 00 01 04 10 40 08 02 80 03 0c 30 41 50 c0 60 90
50: 88 82 a0 46 52 8c b0 c8 57 5d 69 75 d5 99 96 a5
60: 33 be 00 00 00 00 00 a0 00 0a 22 40 00 00 00 00
70: 03 00 10 10 10 10 22 1a 30 10 00 00 00 48 13 3a
80: 3f e4 00 00 a4 00 00 00 00 00 26 00 00 02 1c 00
90: 00 00 00 00 00 00 3c 00 0c 3f 3f 00 d5 99 96 a5
a0: 00 01 04 10 40 08 02 80 03 0c 30 41 50 c0 60 90
b0: 88 82 a0 46 52 8c b0 c8 57 5d 69 75 d5 99 96 a5
c0: 00 01 04 10 40 08 02 80 03 0c 30 41 50 c0 60 90
d0: 88 82 a0 46 52 8c b0 c8 57 5d 69 75 d5 99 96 a5
e0: 00 01 04 10 40 08 02 80 03 0c 30 41 50 c0 60 90
f0: 88 82 a0 46 52 8c b0 c8 57 5d 69 75 02 00 03 01

Here is a register dump that shows signal detect and no CDR lock. Data is not output.

     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f
00: 00 80 84 00 01 01 01 01 60 20 50 6f 08 b4 93 69
10: 3a 20 e0 90 00 13 7a 36 40 20 a0 03 90 00 00 55
20: 00 00 00 40 40 01 6e 00 00 00 30 0f f2 01 00 f6
30: 00 58 11 88 3f 1f 30 00 00 00 00 00 00 00 2c 80
40: 00 01 04 10 40 08 02 80 03 0c 30 41 50 c0 60 90
50: 88 82 a0 46 52 8c b0 c8 57 5d 69 75 d5 99 96 a5
60: 33 be 00 00 00 00 00 a0 00 0a 22 40 00 00 00 00
70: 03 20 00 00 00 00 22 1a 20 10 00 00 00 48 13 3a
80: 00 e4 00 00 a4 00 00 00 00 00 26 00 00 02 1c 00
90: 00 00 00 00 00 00 3c 00 0c 3f 3f 00 d5 99 96 a5
a0: 00 01 04 10 40 08 02 80 03 0c 30 41 50 c0 60 90
b0: 88 82 a0 46 52 8c b0 c8 57 5d 69 75 d5 99 96 a5
c0: 00 01 04 10 40 08 02 80 03 0c 30 41 50 c0 60 90
d0: 88 82 a0 46 52 8c b0 c8 57 5d 69 75 d5 99 96 a5
e0: 00 01 04 10 40 08 02 80 03 0c 30 41 50 c0 60 90
f0: 88 82 a0 46 52 8c b0 c8 57 5d 69 75 02 00 03 01

Thanks for our help,

Greg

Hi Mike,

Do you see anything wrong? Is there something else I can try?

Thanks,
Greg

Hi Mike,

Can the ds125df1610 support 1.92 Gbps. If so what are the register setting?

Thanks,
Greg

Hi Greg,

For the question about 1.92 Gbps operation, the DS125DF1610 will not support this data rate in the normal retimed mode. The CDR is not able to lock at this frequency. You can refer to page 9 of the datasheet for a list of the supported frequency ranges.

However, the device will support this frequency in CDR bypass mode.


Mike Wolfe
DPS APPS / SVA

Hi Greg,

While checking your register settings I see a few register that might be configured incorrectly. Can you list the following features so that I can help to create a programming sequence for you?

- Desired VOD
- Data rate
- Adapt Mode(CTLE only or CTLE+DFE)

I recommend doing a channel register reset, set register 0 bit 2. And then programming the values that I will specify according to your desired settings.


Mike Wolfe
DPS APPS / SVA

Hi Mike,

Thanks for your help.

Desired VOD: 700 mV
Desired Rate: 1.92 Gbps
Adapt Mode: 2, CTLE+DFE

Thanks,
Greg

Hi Mike,

Any progress on the programming sequence?

Thanks,

Greg

Hi Greg,

Since the data rate you would like to operate at is not supported by this device there will be a limitation on the features that you can use. The CDR is required to create clocks for the DFE, FIR and CTLE adaption. If the CDR is not able to lock then these features become unavailable. This means that you will need to operate with manual CTLE configuration and no FIR and DFE.

For application requirements I would use the following sequence:

Register	Write Value	Write Mask	Comment
0xFF	0x00	0xFF	Select share registers
0x02	0x--	0x60	program desired ref clock input frequency
0xFF	0x01	0xFF	select desired channel register set
0xFC	0x--	0xFF
0xFD	0x--	0xFF
0x00	0x04	0x04	reset channel registers, this is self clearing
0x0A	0x0C	0x0C	put CDR into reset
0x14	0x40	0x40	Force signal detect low
0x1E	0x00	0xE0	configure the pfd mux to output raw data
0x09	0x20	0x20	enable override for pfd setting to take effect
0x3D	0x00	0x3F	zero out main cursor
0x3E	0x3F	0x7F	maximize pre cursor and set polarity to true (non-invert)
0x3F	0x00	0x3F	zero out post cursor
0x0D	0x10	0x30	Configure for 700mVpp VOD, set to either 5'h0F or 5'h0E. Bit 4 and 3 go to 0x0D[5:4], bit 2, 1 and 0 go to 0x2D[2:0]
0x2D	0x07 or 0x06	0x07
0x31	0x00	0x60	configure for adapt mode 0
0x03	0x--	0xFF	set desired CTLE value
0x3A	0x--	0xFF
0x0A	0x00	0x0C	release CDR from reset
0x14	0x00	0x40	release signal detect force condition

Some of the items above are precautionary commands and can possibly be removed. Please let me know if you have questions about this sequence.

Mike Wolfe

DPS Apps / SVA

Hi Garrett,

With regard to your question: If the CDR can’t lock (1.92GHz signal is not supported by the CDR module) can we operate the DFE, CDR, FIR in a bypass mode, so that 1.92GHz data can still be routed?

The sequence that Mike Wolfe provided you should allow you to do just what you are requesting. Per the sequence, the PFD mux is being configured for raw data mode (i.e. CDR bypass) and you are zeroing the post and main FIR taps while maximing the pre-cursor (this is the bypass routing scheme for the part.) Moreover you are setting the device to adapt mode 0 and manually entering EQ values. I did notice that the EQ override operation is not included in Mike's sequence. I would add that operation after your write operations to 0x03 and 0x3A.

• To enable EQ override, set channel register 0x2D[3] to '1'

By the way, what are the values that you are programming to registers 0x03 and 0x3A? Perhaps your values need to be adjusted to ensure proper operation. For 1.92GHz there should not be a high amount of EQ boost needed, particularly if the PCB channel is not that long.

Let me know if you have further questions.

Cordialy,

Rodrigo Natal

DPS Applications Engineer

 

We believe the issue is as follows:
If the CDR doesn’t report lock, then the DFE, CDR, FIR will not pass data…
In order to get the CDR to report lock with a 1.92GHz data stream, REF_MODE1 & REF_MODE0 needed to be configured to ‘00’ (referenceless all cap dac, for debug use only).
Initial testing has been successful…

Hi Mitch. I checked this function in the lab using a DS125DF1610 EVM board. When I provide 1.92GHz clock signal as input to DF1610 DUT channel, I can see its Tx output that data after configuring the device to raw mode while still operating in the default ref mode 3. The device does report that CDR is not locked on status register but the raw data output is present.

Regards,

Rodrigo Natal

DPS applications engineer

 

 

Hello

How does the cross point settings affect this? With channel 1 multicast to channels 1 and 2 I see no output without CDR lock. Can this work in a multicast situation?

Thanks,
Greg

Hi,

The datapath flow for the DF1610 device is the following:

EQ -> XPOINT -> DFE -> CDR -> FIR -> Driver

Given the flow above, if you are multicasting channel 1 to channels 1 and 2 then you would need to set both channels 1 and 2 to PFD mux raw mode and adjust FIR tap values accordingly (i.e. zero main and post, max out the pre.)  But once you do that, you should be able to see the data output on both channels for the default ref mode 3. I've double checked this on the bench with my DF1610EVM to confirm that I'm able to do it while passing 1.92GHz 1010 signal.

Regards,

Rodrigo Natal

DPS Applications Engineer

Hi Rodrigo,
Thanks for your help.
What did you set registers 0x96 and 0x9b to? Does channel 2 need to be a slave?

Thanks,
Greg

Hi Greg,

For my setup I set:

• channel being multi-casted (in my case it is channel 4A) - 0x96 set to 0x1C and 0x9B set to 0x00
• channel receiving data from multi-cast (in my case channel 5A) - 0x96 set to 0x1C and 0x9B set to 0x00

Cordially,

Rodrigo Natal

DPS Applications Engineer

Hi Greg, Garrett,

Were you able to resolve this issue?

Mike Wolfe

DPS APPS / SVA

Hi Rodrigo,

Thanks for your help.

Does this work if channel 5A is configured to operate as a slave (0x96 set to 0x3c). If not, why? When would slave mode be used?

Thanks,

Greg

Hi Greg,

You should always configure channel register 0x96 bit 5 to be master. Actual master control is assigned by mux selection. Slave mode is indeed intended for the scenario where the device is configured to have one-to-many connections and the channel in question is outputting data input to another channel. However, based on our functional verification we recommend always setting register 0x96 bit 5 for master (i.e. value of '0'.)

Rodrigo Natal

DPS Applications Engineer